Sequential Logic

Question 1

How is instruction execution coordinated?

Answer 1

A sequence of micro steps coordinated by a clock.

Question 2

How do we coordinate input across a shared bus?

Answer 2

All the different components can read from the same bus

they just need to be made active by a signal line from the control unit (CU)

Question 3

What does the input received in a component generally go through?

Answer 3

A buffer

Question 4

What does a buffer do

Answer 4

It outputs the same input but it is used for making the signal stronger, ie if one component trying to output to many other components it would give a weak signal

Question 5

What does a tristate buffer do?

Answer 5

Can set the output voltage to either high or low, allows multiple device to share the bus as only on of the outputs is enabled to set the voltages.

Question 6

What controls, what components read and what component outputs?

Answer 6

The Control Uni (CU)

Question 7

What is the scratchpad?

Answer 7

Scratchpad consists of 16 locations storing 4 bit values, the 16 locations require 4 bit addresses to address them from 0000 to 1111

Question 8

How do we store 1 bit using logic circuits?

Answer 8

Take two back to back inverters. Circuit only has two possible states(known as a bistable element) This circuit forms static memory because it is stable

Question 9

How do we add write capability to the memory unit?

Answer 9

replace an inverter with a NOR gate connecting NOT Q and R. R stands for reset, when R is set to 1 Q is set to 0, effectively resetting its value, NOT Q is then set to 1 so even when R is set back to 0 the NOR gate will still output a 0 for Q

Question 10

How does and RS latch work?

Answer 10

An RS latch consists of two NOR gates connected to R and NOT Q and Q and S. When S is set to 1 NOT Q is set to 0 which then sets Q to 1, When R is set to 1 Q is set to 0. R resets the value, S sets the value, the latch refers to the memory being retained after S or R reverts back to 0.

Question 11

How many stable states are there in a RS latch and what is an unstable state?

Answer 11

4, an unstable state is when R and S is set to 1 resulting in Q and NOT Q being 0

Question 12

What is a D latch also known as>

Answer 12

A transparent latch

Question 13

How does a D latch work?

Answer 13

Stores 1 bit value of D when the clock is high, latch is transparent to D value when the clock is high, also eliminates the R=S=1 problem.

Question 14

Draw a D Latch logic circuit?

Answer 14

DRAW

Question 15

What is a D flip flop?

Answer 15

Stores 1 bit of data which is set only on the clocks rising edge.
Consists of “master” and “slave” D latches where the data value only gets through on the rising clock edge.

Question 16

What is used to indicate that the D value is only passed on the rising edge?

Answer 16

A little downward facing triangle on the top

Question 17

What is an enabled Flip Flop?

Answer 17

a 2 input multiplexer can be used to only select the D input when the flip flop is enabled high. If it is low the current value of D is just passed back into the flip flop.

Question 18

What does EN indicate on the diagram?

Answer 18

That the flip flop needs to be enabled for the D value to be updated

Question 19

What does a 4 bit register look like using D flip flop’s, what about 4 1 bit memory?

Answer 19

Each d flip flop has an individual data line, and has one negated write connected to a generated enabled across all of the flip flops.
One data line and 4 individual write lines are connected to each flip flop

Question 20

How is output enabled from a memory block?

Answer 20

A tristate buffer(with active low) puts the output of one 2 bit store onto bus.

Question 21

How are the output signals from the CPU translated into read and write controls fro different blocks?

Answer 21

Read control activates the read lines, the write control activates the write lines. 1 bit address decoding logic for accessing the two 2 bit memory.

Question 22

Describe how a memory cell can be addressed?

Answer 22

In rows and columns(using active low signals) NOT row NOT column NOT w needed to pass 0 into NOT enabled to write, same for read.

Question 23

Construct a scratchpad from memory blocks

Answer 23

Use 4 16X1 memories in parallel to provide 16X4 memory. Each memory is connected to a different data bus line. All read write and address are connected across same lines, only data value is different.