Structure and Function of the Processor

Question 1

What is the ALU?

Answer 1

The ALU (Arithmetic and Logic Unit) completes all of the arithmetical and logical operations.

Can perform shift operations also.

Logical operations include boolean logic operations such as AND, OR, NOT, and XOR.

Question 2

What is the control unit?

Answer 2

directs the operations of the CPU. It has the following jobs:

Controlling and coordinating the activities of the CPU
Managing the flow of data between the CPU and other components
Accepting the next instruction
Decoding instructions
Storing the resulting data back in memory

Question 3

what is a register

Answer 3

Registers are small memory cells that operate at a very high speed.

Question 4

purpose of register

Answer 4

They are used to
temporarily store data and all arithmetic, logical and shift operations occur in these
registers.

Question 5

job of the program counter

Answer 5

holds address of next instruction to be executed
It sends the address to the MAR, before being incremented, and pointing to the next address.

Question 6

job of accumulator

Answer 6

its a general purpose register

Stores the results from calculations

Question 7

job of memory address reg

Answer 7

Holds the address of a location that is to be
read from or written to.
This address was copied from the PC.

Question 8

job of mem data reg

Answer 8

Temporarily stores data that has been read
or data that needs to be written to memory.

Question 9

job of current instruction reg

Answer 9

Holds the current instruction being
executed, divided up into operand and
opcode.

Question 10

width of bus

Answer 10

The width of the bus - num of parallel wires the bus has.

directly proportional to the number of bits that can be transferred simultaneously at any given time.

Question 11

typical bus widths

Answer 11

buses are typically 8, 16, 32 or 64 wires wide.

Question 12

what are buses

Answer 12

Buses are a set of parallel wires which connect two or more components inside the CPU.
There are three buses in the CPU: data bus, control bus, and address bus. These buses
collectively are called the system bus.

Question 13

data bus

Answer 13

This is a bi-directional bus (meaning bits can be carried in both directions). This is used for
transporting data and instructions between components.

Question 14

control bus

Answer 14

This is a bi-directional bus used to transmit control signals between internal and external
components. The control bus coordinates the use of the address and data buses and
provides status information between system components.

Question 15

address bus

Answer 15

This is the bus used to transmit the memory addresses specifying where data is to be sent
to or retrieved from. The width of the address bus is proportional to the number of
addressable memory locations.

Question 16

control signals of control bus

Answer 16

bus request
Bus grant
Memory write
Memory read
Interrupt request:
Clock

Question 17

A LEVEL ONLY - PIPELINING

Answer 17

process of completing the fetch, decode, and execute cycles of three
separate instructions simultaneously, holding appropriate data in a buffer in close proximity
to the CPU until it’s required.

While one instruction is being executed, another can be
decoded and another fetched.

Question 18

what is fetch decode eecute cycle

Answer 18

The fetch-decode-execute cycle is the sequence of operations that are completed in order
to execute an instruction.

Question 19

aim of pipelining - A LEVEL ONLY

Answer 19

Pipelining is aimed to reduce the amount of the CPU which is kept idle.

Question 20

what is pipelining seperated into

Answer 20

instruction pipelining
arithmetic pipelining

Question 21

instruction pipelinning

Answer 21

Instruction pipelining is separating out the
instruction into fetching, decoding, and executing.

Question 22

arithmetic pipelining

Answer 22

Arithmetic pipelining is breaking down
the arithmetic operations and overlapping them as they are performed

Question 23

decode phase

Answer 23

Decode phase: -
The contents of CIR are split into operand and opcode

the data/instruction is decoded and processed

Question 24

fetch phase

Answer 24

Fetch phase: -
Address from the PC is copied to the MAR —
Instruction held at that address is copied to MDR by the data bus
Simultaneously, the contents of the PC are increased by 1
The value held in the MDR is copied to the CIR

Question 25

amount and type of cache mem

Answer 25

Cache memory is the CPU’s onboard memory. Instructions fetched from main memory are copied to the cache, so if required again, they can be accessed quicker. As cache fills up, unused instructions are replaced.

Question 26

execute phase

Answer 26

Execute phase: - The decoded instruction is executed opcode carried out on the operand

Question 27

lev 2 cache

Answer 27

Relatively fast memory cell, with a medium sized capacity. (256KB-2MB)

Question 28

num of cores

Answer 28

A computer with multiple cores can complete more than one fetch-execute cycle at any given time. However, not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this is not always possible.

Question 29

what is a core

Answer 29

A core is an independent processor that is able to run its own fetch-execute cycle.

Question 30

Why is it that a dual core results in apporximately below 2x speed

Answer 30

The cores need to communicate w/ each other which takes time

Question 31

Why sometimes multicore is not possible

Answer 31

However, not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this is not always possible.

Question 32

factors affecting cpu performace

Answer 32

There are three factors that affect CPU performance: clock speed, number of cores and the amount and type of cache memory.

Question 33

clock speed

Answer 33

The clock speed is determined by the system clock. This is an electronic device which generates signals, switching between 0 and 1. All processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1. The clock speed is the time taken for one clock cycle to complete.

Question 34

lev 1 cache

Answer 34

Very fast memory cells with a small capacity. (2-64KB)

Question 35

von neumann architecture

Answer 35

This architecture includes the basic components of the computer and processor (single control unit, ALU, registers and memory units) in which a shared memory and shared data bus is used for both data and instructions. Von Neumann architecture is built on the stored program concept.

Question 36

lev 3 cache

Answer 36

Much larger and slower memory cell.

Question 37

harvard achitecture - A LEVEL ONLY

Answer 37

Harvard architecture has physically separate memories for instructions and data, more commonly used with embedded processors.This is useful for when memories have different characteristics, i.e. instructions may be read only, while data may be read-write. This also allows you to optimise the size of individual memory cells and their buses depending on your needs, i.e. the instruction memory can be designed to be larger so a larger word size can be used for instructions.

Question 38

advantages von neumann arch

Answer 38

Cheaper to develop as the control unit is easier to design Programs can be optimised in size

Question 39

what is key aspects of von neumann arch

Answer 39

MAR MDR Program counter accumulator Bus ALU control unit

Question 40

contemporary processing

Answer 40

Contemporary processors use a combination of Harvard and Von Neumann architecture. Von Neumann is used when working with data and instructions in main memory, but uses Harvard architecture to divide the cache into instruction cache and data cache.

Question 41

advantages harvard arch - A LEVEL ONLY

Answer 41

quicker execution as data and instructions can be fetched in parallel. memories can be different sizes, which can make more efficient use of space

Question 42

wHATS THE system bus

Answer 42

the collection of the data bus, address bus and control bus

Question 43

What is the width of a bus?

Answer 43

Num of parallel wires it has

Question 44

What does adding a wire to the address bus do to the number of addressable locations

Answer 44

2x num of addressable locations

Question 45

Bus Request

Answer 45

bus request: shows that a device is requesting the use of the data bus

Question 46

Bus grant

Answer 46

Bus grant: shows that the CPU has granted access to the data bus

Question 47

Memory write

Answer 47

Memory write: data in the data bus is written into the addressed location

Question 48

Memory read

Answer 48

Memory read: data is read from an addressed location to be placed onto the data bus

Question 49

Interrupt Request

Answer 49

Interrupt request: shows that a device is requesting access to the CPU

Question 50

Clock

Answer 50

Clock: used to synchronise operations

Question 51

the 5 registers used in FDE

Answer 51

PC MDR MAR CIR ACC

Question 52

what is memory divided up into equal units of

Answer 52

Words

Question 53

word lengths

Answer 53

8,16,32,64bit The word length is the number of bits that can processed in one cycle

Question 54

what does each word have

Answer 54

seperate mem address