Test 1 Flashcards
(259 cards)
1
Q
Who discovered electrons?
A
Lorentz
2
Q
When were electrons discovered?
A
1895
3
Q
Who invented vacuum tubes?
A
De Forest
4
Q
When were vacuum tubes invented?
A
1906
5
Q
Who invented the BJT?
A
Shockley, Bardeen, and Brattain (awarded Nobel Prize)
6
Q
What does BJT stand for?
A
Solid-state discrete Bipolar Junction Transistor
7
Q
When was the BJT invented?
A
1950
8
Q
Who invented integrated circuits and the monolithic (or planar) process?
A
Robert Noyce and Jack Kilby
9
Q
When were integrated circuits invented?
A
1958
10
Q
Who invented the FET?
A
Bell Labs
11
Q
When was the FET invented?
A
1960
12
Q
What does FET stand for?
A
Field effect transistor
13
Q
What kind of charge do neutrons carry?
A
None
14
Q
What kind of charge do protons carry?
A
Positive
15
Q
What kind of charge do electrons carry?
A
Negative
16
Q
How much heavier than electrons are protons and neutrons?
A
1800 times
17
Q
What are the three elements of a circuit?
A
A group of electrical components connected by elecrical wires powered by a power supply.
18
Q
What are some typical electical components (devices)?
A
Transistors, resistors, capacitors, diodes, inductors
19
Q
What are some typical materials for electrical wires in IC?
A
Copper, aluminum
20
Q
What are some typical power supplies?
A
Battery, household power outlets
21
Q
What is a conventional (discrete) circuit?
A
All electrical components and wires are manufactured seperately (individually). Components are connected with wires through soldering.
22
Q
What are integrated circuits?
A
All electrical components and wires are built and manufactured over the surface of a tiny piece of silicon.
23
Q
What is a schematic?
A
A circuit drawing which shows details of building a circuit
24
Q
What are the details of a schematic?
A
Types and number of components to use, and how to connect (hookup) these components.
25
What is a logic symbol?
A symbolic shape used to represent a functional circuit.
26
What are the two main categories of electrical devices?
Active and passive
27
Name some active devices.
Transistors, diodes
28
Name some passive devices.
Resistors, capacitors, inductors
29
What characteristic distinguishes active devices from passive ones?
Active devices can amplify.
30
What are the two main types of transistors?
MOSFETs and BJTs
31
What does MOSFET stand for?
Metal oxide semiconductor field effect transistor
32
What are the two types of MOSFETs? Give four different names.
P-channel MOSFET, PMOS, P-gate, pfet / N-channel MOSFET, NMOS, N-gate, nfet
33
What are the two types of BJTs?
NPN and PNP
34
Describe the symbols for the passive devices
Resistor = sawtooth / capacitor = break in line with T and bow / inductor = round tooth
35
What does the symbol for a diode look like?
Triangle with a line across the point (like an inverter with a line instead of a bubble)
36
How are diodes related to transistors?
A diode is a partial transistor with the collector not used.
37
What are the four terminals of a MOSFET?
Source, drain (interchangeable), gate, bulk
38
What are the three terminals of a BJT?
Collector, emitter, base (none interchangeable)
39
What are the three main types of integrated circuits?
CMOS (only MOSFETS and passive devices), BJT (only BJT and passive devices), BiCMOS (BJT + CMOS + passive devices)
40
What are two other names for a transmission gate?
Transfer gate, CMOS switch
41
What is an AND group / configuration?
Two or more transistors of the same type connected in series
42
What is an OR group or configuration?
Two or more transistors of the same type connected in parallel.
43
What is an electrical conductor?
A medium through which an electrical current can flow.
44
What are electrical conductors made of in IC?
Metal or semiconductor
45
What semi-conducting materials are used in IC?
poly, diffusions, nwell, and p-substrate
46
What non-conducting materials are used in IC?
Silicon Dioxide and Silicon Nitride
47
What is the chemcial symbol for Silicon Dioxide?
SiO2
48
What is the chemical symbol for Silicon Nitride?
Si3N4
49
What are other names for an electrical wire?
Node, net, signal, bus, line
50
What are names for a label associated with a wire?
Node name, wire name, net name, signal name
51
What is an electrical short?
When two conductors having different node names are accidentally connected (shorted) together
52
Is short always bad?
No short might just refer to a correct connection
53
What is a floating net?
Wires that the designer forgot to join
54
When is a conductor open?
When there is a break in connection
55
Is open always bad?
No, it can just refer to correctly breaking a node
56
What is the process called to fabricate an IC?
Planar or monolithic
57
What is the very top layer of insulator called on an IC?
Passivation layer
58
What is another name for an insulating material?
Dielectric
59
What are other names of the oxide layers?
CVD oxide, gate oxide, field oxide
60
What are the two ways of connecting materials?
Touching (or merging) materials of the same layer, or allowing materials at two adjacent levels to meet (touch) through a hole in the insulator
61
What are global nets?
Nets that travel everywhere on the chip and are heavily loaded
62
When should an AND be interpreted as a primitive logic?
When its load is not an OR or a NOR
63
When should an OR be interpreted as a primitive logic?
When its load is neither an AND nor a NAND
64
What are the benefits of complex logics?
Reduction in transistor sizeMore compact and simpler layoutTime saving in doing layoutCircuit speed improvementReduction in circuit power consumption
65
Steps to convert complex logic?
1. Is this a complex logic?2. Identify final output (NAND or NOR), and draw it as primitive3. Identify logic symbols driving that primitive4. Replace each NMOS in the primitive with the correct AND or OR group5. Replace each PMOS with the complementary AND or OR group6. Correctly connect polys7. Repeat steps for each logic symbol in #3
66
Define cell.
A piece of layout drawing
67
Define block
A larger cell
68
Define mega cell or macro cell
A relatively large piece of layout, usually made of several smaller cells or blocks
69
Define die
An entire layout project or an actual design (chip) in silicon form. One die contains one project on it
70
Define die size
The physical dimension of a die. Normally measured in mills or microns
71
Define SSI
Small scale integration - small chips
72
Give an example of a SSI
The power management chip on a cell phone
73
Define MSI
Medium Scale Integration
74
Define LSI
Large Scale Integration
75
Define VLSI
Very Large Scale Integration
76
Define ULSI
Ultra Large Scale Integration
77
Give an example of a ULSI
A pentium chip
78
Define SOC
System on a chip - mega chips
79
Define tape out
The time when a project is completed
80
Define cell-library
Layout database which contains a collection of cells, blocks, etc., with unique cell names bundled together under a project (library) name
81
What is one millimeter relative to a meter?
1/1000 of a meter 10-3
82
What is one micrometer relative to a meter?
1 / 1,000,000 of a meter 10-6
83
What is one nanometer relative to a meter?
1 / 1,000,000,000 of a meter M-9
84
What's one angstrom?
1 / 10,000,000,000 of a meter 10-10
85
What's one milli-inch?
1 / 1000 of an inch 10-3 inch
86
What the abreiviation for millimeter?
mm
87
What's the abbreviation for micron?
um
88
What's the abrieviation for nanometer?
nm
89
What's the abbrieviation for angstrom?
A with a little circle over it
90
What's the abbreviation for a milli-inch?
mil
91
How many microns in 1 mil?
25.4
92
How many feet in 1 meter?
3.2808...
93
What's another name for micrometer?
micron
94
What's another name for micron?
Micrometer
95
What's a PN junction?
Formed when P- or P+ touches N- or N+
96
When is a PN junction forward-biased?
When the P-material sees a higher voltage (potential) than the N-material does.
97
When is a PN junction reverse-biased?
When the P-material sees a lower voltage than the n-material does
98
What are other names for reverse-biased?
Back biased, reverse connected
99
What is formed when a PN junction is reverse-biased?
A depletion layer, which blocks the flow of current
100
What is the nwell typically connected to?
VDD
101
What is the p-substrate typically connected to?
VSS
102
Why must the nwell and p-substrate be connected to VDD and VSS?
To electrically isolate the nwell and p-substrate, so that operations of the p-gates does not interfere with operation of the n-gates and vice-versa
103
What would happen if you put a p-gate in a p-substrate?
The source and drain would short together
104
What are other names for the bulk?
Back-gate, body, 4th gate
105
What are other names for ptap?
P-substrate-tap, P-substrate-tie, P-substrate-strap, tie-down
106
What are other names for the ntap?
nwell-tap, nwell-tie, nwell-strap, tie-up
107
What is a DRC width check?
Minimum distance between inside edge and inside edge of same layer
108
What is a DRC spacing check?
Minimum distance check from outside edge to another outside edge of same layer. Also applies to corner to corner check, the notch check, and the donut hole check.
109
What is a fat metal rule?
Accounts for manufacturing difficulties as a result of the loading effect etch that can lead to issues like larger line edge roughness. Plasma etching. Line quality is better for thinner metals.
110
What is an extension check?
Minimum distance of one layer extending beyond the edge of another layer. This is a distance check of an inside edge to an outside edge.
111
What are other names for extension check?
Overhang check, end-cap check
112
What is the enclosure check?
A check that one layer completely surrounds another layer by a minimum distance. Distance check of an inside edge of a layer to an outside edge of another. The layer with the outside edge must be completely inside the other layer.
113
What's an area check?
The minimum area check of a layer in um^2
114
What's an intersection check?
Minimum distance of one layer overlapping another. Inside edge to inside edge check.
115
What's another name for intersection check?
Overlap check.
116
What does CIW stand for, and what does it do?
Command Interpreter Window. The first window that appears when you start Cadence. Controls the software.
117
Where do Cadence messages appear?
In the CIW message window
118
Where do messages from the current command appear?
In the CIW prompt line
119
What is the CIW input line for?
Typing in SKILL functions or enter coordinates
120
What does the ampersand mean in icfb&?
Run in background
121
Where can you set up and toggle the icon menu, mouse settings line, and prompt line?
CIW->Options->User Preferences
122
What does LSW stand for?
Layer and Selection Window
123
What is the LSW for?
Chosing design layer, make objects visible or invisible, or make objects selectable or unselectable.
124
How do you open the library browser?
CIW->tools->library browser
125
What does the title bar of the cellview window display?
Info about the cell you're viewing, including lib, cell, view name
126
What does the status banner do?
Displays info about the cursor, selection, points, and command
127
What do you use the cursor and pointer for?
Cursor to enter points or select design objects. Pointer to select menu items of options in command forms
128
What does the promptline do in the Layout Cellviews window?
Shows instructions from the current command.
129
What does the Tools menu do?
Lists available Cadence apps. The list differs depending on what you've purchased.
130
What does the Design menu do?
Save or discard design changes, move within design hierarchy, plot a design, or set defaults.
131
What does the Window menu do?
Change the appearance of the cellview, or change what you are viewing in this cellview.
132
What does the Create menu do?
Draw shapes of place cell instance, devices, contacts, labels, or pins.
133
What does the Edit menu do?
Move, copy, modify, delete or search for objects in this cellview
134
What does the Verify menu do?
Run various verification checks on the design in this cellview
135
What does the Misc menu do?
Perform additional editing tasks or display additional data about this cellview
136
What options are in the Layout Editor popup window?
Instance..., Move, Copy, Delete, Properties...
137
What does the Display Options form do?
Controls the appearance of objects and the behavior of commands in this cellview.
138
How do you open the Display Options form?
Design->Options->Display or Type 'e'
139
What Display controls can you toggle in the Display Options window?
Nets, Access Edges, Instance Pins, Array Icons, Label origins, Dynamic Hilight, Tiny Inst Detail, Axes, Path borders, Instance Origins, EIP surround, Pin Names, Dot Pins
140
Where can you specify the exact range of display levels?
Display Controls ('e')
141
Where can you set features of the grid?
Display Controls ('e')
142
What layer properies are shown in the LSW?
Layer stipple pattern and color, Layer name, Layer purpose
143
What are common layer purposes?
dg = drawing (most common) wg = warning, er = errors, nt = net, t0 = tool0, t1 = tool1, etc.
144
What are the four buttons in the LSW?
AV = All Viewable, NV = Not Viewable, AS = All Selectable, NS = Not Selectable
145
How do you toggle the visibility of an individual layer in the LSW?
MMB
146
How do you toggle an individual layer's selectibility in the LSW?
RMB
147
What is the Show Layers form?
Allows you to show / hide Instances, pins, and a few other layers and objects
148
What is our Assura DRC rules file called?
assuraDRC.rul
149
What is a reference libraray?
As opposed to working library. a read-only library.
150
What is a cell call?
The operation of creating an instance.
151
What is a master cell?
The cell an instance is linked to.
152
What are the benefits of instances?
1. Reuse existing cells without having to redraw them2. Instant updates when master cell is modified3. Save memory and disk space.
153
What's a mosaic?
A layout object which is formed by a 1 or 2-d duplication of ONE instance.
154
What's the current cell?
The cell that's currently being edited.
155
What's the top cell?
The cell which is initially opened from a library.
156
What are other names for top cell
Primary cell, level 0 cell
157
What's a master name?
Cell name as it's used in a library
158
What's an instance name?
Unique name assigned to every instance. Automatically created and can be overwritten.
159
What's hard-data?
Objects that aren't instances or arrays.
160
What's another name for hard data?
Hand-drawn objects.
161
What's another name for mosaic?
Array
162
What's a flat-cell?
Contains no instances or arrays. Nothing but hard-data.
163
What are leaf-cells?
Misc small cells used together with big blocks
164
What does descend mean?
Opening a master cell by going down from the parent cells through the hierarchy. One decend take you down one level at a time.
165
What does edit-in-place mean?
Same as descend, except goes to any level instead of down only one level. Allows you to see all other levels while editing.
166
What does make cell mean?
Push some objects one level below the current one. A new cell containing those objects will be created in your library.
167
What does flatten mean?
Reverse of make cell. Raises objects one level up.
168
What does stream out mean?
Converts proprietary layout data-base format to an industrial standard layout database format.
169
What is stream in?
Converts a standard layout format to a proprietary one.
170
What does Update Instances do when copying?
Allows resetting of references points for copied instances and arrays.
171
What is the Transistor Channel Width (W)?
The distance between the two diffusion edges of a MOSFET active gate area
172
What is the Transistor Channel Length (L)?
Distance between the two poly edges of a MOSFET active gate area.
173
What are three common ways to show transistor (gate) sizes?
1. W/L ratio - 20/0.1 means W= 20 um, L = 0.1 um2. W=, L= - W= 20 u, L = 0.1 u3. M factor - W = 5u L = 0.1u M=4 (multiplication factor)
174
How do you turn on an NMOS?
Apply voltage (such as VDD) higher than that of the bulk. This creates an Electric Field Effect, which attracts electrons to form a channel of carriers across the N+ terminals.
175
How do you turn on a PMOS?
Apply voltage (such as VSS) lower than that of the bulk. This creates an Electric Field Effect, which attracts holes to form a channel of carriers across the P+ terminals.
176
What is the transistor (gate) strength equation?
Ids = (u E0 ESio2 W / Tox L) X [a function of the gate voltage]Ids = current between D & S terminalsu = surface mobility of charge carriersE0 = Permittivity of vacuumESio2 = Dielectric constant of SiO2Tox = Gate oxide thicknessW = channel widthL = channel length
177
What is the surface mobility of electrons?
~500 cm^2 / v-sec
178
What's the surface mobility of holes?
~300 cm^2 / v-sec
179
Why are PMOSes weaker than NMOSes?
Because the surface mobility (u) of holes is lower, and that's part of the numerator in the gate strength equation.
180
What is the standard permittivity value?
8.85 x 10-3 fF/um
181
What is another name for the dielectric constant?
Relative Permittivity
182
What's the definition of the dielectric constant?
The measure of a material's ability to resist the formation of an electric field within it, relative to a vacuum's ability to resist the formation of an electric field.
183
What's the dielectric constant of SiO2?
3.9
184
What size is the gate oxide thickness?
~200 angstroms
185
How do W and L relate to a gate's strength?
The larger the W, the stronger the gate. The smaller the L, the stronger the gate.
186
What's a finger gate?
A transistor that's been split into multiple segments (or fingers) and these segments are the reconnected back together to form the required W/L ratio.
187
What are other names for finger gates?
Interdigitated gates, Split Gates, Folding Gates, Legged Gates.
188
Beneftis of finger gates:
1. Fit into specific areas2. Speed improvement due to reduced total diffusion areas (reduced capacitance) and due to reduced resistance because of the shortening of poly lines.3. Mandatory in many matching transistor layouts.
189
What is the only correct way to layout finger gates in series in Analog circuits?
Split each mosfet individually and connect those groups in series.
190
What technology are we using in school?
.1um 5 layer metal BiCMOS nwell process
191
How do proton and neutron masses relate?
Almost the same
192
How do electron and proton charges relate?
Almost same charge, with reversed polarity
193
What are other names for device terminals?
Legs, pins, leads
194
What is another name for devices?
Discrete components
195
What are examples of good conductors?
Copper, Aluminum, Gold, Silver
196
What are examples of poor conductors?
Plastic, wood, air, silicon dioxide SiO2, silicon nitride (Si3N4)
197
What's poly short for?
Polycrystalline silicon
198
How many valence electrons does silicon have?
4
199
How many valence electrons does boron have?
3
200
How many valence electrons does arsenic have?
5
201
How many atoms does pure silicon have?
5x10^22 per cm^3
202
What do N, N+, and N- mean?
silicon doped with arscenic, N = moderate, N+ = very high, N- = very light
203
What are the silicon-related layers (base layers)?
p-substrate, nwell, diffusions, oxide, poly
204
When can you share diffusion?
Same node name, same material type
205
Who builds the actual masks?
Mask vendor / mask shop
206
What is the symbol for charges?
Q
207
What is the unit of measurement of charges?
coulombs (C)
208
What is the definition of charges?
Amount of electricity
209
What's the definition of voltage?
Difference in potential
210
What is the symbol for voltage?
V
211
What are other names for voltage difference?
potential difference, electro-motive force (emf)
212
What is the symbol for electrical current?
I
213
What is electrical current?
Charges moving along a conductor
214
What is the unit of measurement for current?
Amperes (A), which is number of coulumbs per second
215
What determines which way current flows?
Always from higher to lower voltage.
216
What are the ends of a diode called?
anode (p side), cathode (n side)
217
What are majority and minority carriers?
p-material, holes are the majority, n-material, electrons are the majority
218
Steps to connect an nwell to certain potential
1. Draw at least one piece of ndiff inside the nwell2. Draw at least one contact on each ndiff3. Draw piece of m1 covering that contact.4. Connect m1 to correct node name.
219
Guidelines for laying out taps (5 items)
1. More taps the better if time and space is available.2. More contacts on each tap the better if time and space is available.3. Each device is required to see a tap within 5 um.4. Taps closer to the divide the better.5. Best location is between pmos and nmos. Increases isolation / separation bewteen nwell and p-substrate. Thicker depletion layer.
220
What is a guard ring?
Lots of taps around a device
221
Why the spacing rules?
Overcome misalignment errors
222
Define pitch
Minimum width + minimum spacing.
223
What percentage of layers are drawn layers?
About 2/3. 1/3 generated layers / CAD layers.
224
What is the general name for companies like Cadence?
EDA - Electronic Design Automation company
225
How much does virtuoso cost?
$30k per seat / $80k advanced
226
What does DFII stand for?
Design Framework II
227
What are the files called that come from the manufacturer?
Tech files, technology files
228
What does PDK stand for?
Process Design Kit
229
What is the extension of the file to compile when creating a new library?
.tf
230
What is the off grid issue?
When diagonal lines or circles cause vertices to not line up with the grid
231
What is the panic file?
In case of power loss, etc, can be recovered from command line.
232
What are the five ways to enter a command in the layout editor?
MenuOn-screen iconsBind KeyStroke Gesturecommand line
233
What is the reference point?
Shows last click
234
What is the INFIX option?
When on, no click is necessary for first point
235
Where is the INFIX option?
CIW->Options->user preferences
236
What is window stretch
Stretching two or more edges.
237
What does PDV stand for?
Physical Design Verification
238
What does DRC stand for?
Design Rule Check
239
What are other names for the DRC rule files?
rule set, rule deck, command files
240
What are examples of DRC programs?
Assura, Diva, Dracula
241
How do you run DRC?
Layout editor->Assura->Run DRC...
242
What are issues when drawing polygons?
re-entrant issue, self-intersecting issue, no acute angles
243
What are chopped corners called?
chamfers
244
What are the three big EDA companies?
Cadence, Mentor, Synopsys
245
What are smaller EDA companies?
Tanner - ledit / Springsoft - Laker
246
What does LVS stand for?
Layout Versus Schematic
247
What are the two standard layout formats?
GDS and CIF
248
What does GDS stand for?
Graphical Display Screen (the most common standard layout format)
249
What does CIF stand for?
Caltech Intermediate Form, the newer (but less common) layout format
250
Who made the first layout machine?
Calma Design Systems
251
When is it appropriate to use stream in / out instead of import / export?
With GDS files. CIF files you should use import / export
252
What are alternate names for GDS files?
stream files, calma files
253
What are common file extensions for GDS files?
.gds .sf .gds2 .st
254
What are three things you need to set when streaming out?
1. Which layout2. GDS filename3. Layer map file (sdi_stream.map)
255
What are two common warnings after streaming out?
Layer not being exported, lables translated on stream font 0
256
What are things you need to set up when streaming in?
1. Where and name of GDS file2. Name of library3. Top cell name4. Layer map file (sdi_stream.map)
257
What's another name for the active gate area?
transistor area
258
What does surface inversion mean, and when is a mosfet working in inversion mode?
Surface inversion is when the material between source and drain becomes a conductive channel - N- becomes P+, or P- becomes N+ So a mosfet is working in inversion mode when it's on.
259
What is PIPO.LOG for?
Logs all statistical information about stream-out or stream-in operation. Also contains info about warnings and errors.
