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OCR A LEVEL Computer Science > Topic 1.1 > Flashcards

Topic 1.1 Flashcards

The characteristics of contemporary processors, input, output and storage devices (54 cards)

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1
Q

Examples of arithmetic operations

A

Add
Subtract
Multiply
Divide

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2
Q

Examples of control signals

A

Bus request
Bus grant
Memory write
Memory read
Interrupt request
Clock

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3
Q

Examples of logic operations

A

AND
OR
NOT
XOR

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4
Q

Function of the accumulator

A

Stores the results from calculations

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5
Q

Function of the CIR

A

Holds the current instruction being executed, divided up into operand and opcode

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6
Q

Function of the MAR

A

Holds the address of a location that is to be read from or written to

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7
Q

Function of the MDR

A

Temporarily stores the data that has been read or data that needs to be written

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8
Q

Function of the PC

A

Holds the address of the next instruction to be executed

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9
Q

How does pipelining work

A

The process is split into instruction pipelining and arithmetic pipelining, and they carry out the appropriate tasks

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10
Q

How is assembly language executed

A

The instruction is divided into operand and opcode in the CIR

The operand contains the data/address upon which the operation is to be performed

The opcode specifies the type of instruction to be executed

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11
Q

Jobs the control unit has ( maybe remember just a few)

A

Controlling and coordinating activities of the CPU

Managing the flow of data between the CPU and other devices

Accepting the next instruction

Decoding instructions

Storing the resulting data back in memory

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12
Q

What are buses

A

A set of parallel wires that connect 2 or more components

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13
Q

What are registers

A

Small memory cells within the CPU, which
operate at a very high speed and are used to temporarily store data

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14
Q

What are the 3 types of buses

A

Data bus
Address bus
Control bus

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15
Q

What are the main 3 factors affecting CPU performance

A

Clock speed
Number of cores
Cache memory

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16
Q

What does the control bus do

A

Coordinates the use of the address buses and data buses and provides status information between system components

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17
Q

What happens in the fetch phase of an FDE cycle

A

The address from the PC is copied to the MAR

The instruction held at the address is copied to the MDR by the data bus

Simultaneously, the contents of the PC are increased by 1

The value held in the MDR is copied to the CIR

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18
Q

What is a bus grant

A

Shows that the CPU has granted access to the data bus

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19
Q

What is a bus request

A

Shows that a device is requesting the use of the data bus

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20
Q

What is a clock

A

Used to synchronise operations

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21
Q

What is a control bus

A

A bi-directional bus used to transmit control signals between internal and external components

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22
Q

What is a core

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A

An independent processer that is able to run its own FDE cycle

23
Q

What is a interrupt request

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A

Shows that a device is requesting access to the CPU

24
Q

What is a system clock

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A

An electronic device that determines clock speed and generates signals

25
What is arithmetic pipelining
Breaking down the arithmetic operations and overlapping them as they are performed
26
What is assembly language
A code that uses mnemonics to represent instructions Eg. ADD represents addition
27
What is clock speed
The time taken for one clock cycle to complete
28
What is instruction pipelining
Seperating out the instruction into fetching, decoding, and executing
29
What is meant by the width of the bus
The number of parallel wires the bus has Bus width is directly proportional to the number of bits transferred Eg. 8 , 16 , 32 or 64 wires wide
30
What is memory read
Data is read from a specific location to be placed onto the data bus
31
What is memory write
Data is written into the addressed location using this bus
32
What is pipelining
The process of completing fetch-decode-execute cycles of 3 separate instructions simultaneously
33
What is the address bus
The bus used to transmit memory addresses (Specifies where data is to be sent or retrieved from) The width of the address bus is proportional to the number of addressable memory locations
34
What is the ALU
Arithmetic logic unit Completes arithmetic and logical operations
35
What is the control unit
The component of the CPU that directs its operations
36
What is the CPU
The brain of the computer It executes instructions that allow programs to be run
37
What is the data bus
A bi-directional bus This means bits can be carried in both directions Used to transport data and instructions between components
38
What is the FDE cycle
A sequence of operations that are completed in order to execute an instruction
39
What occurs in the decode phase of an FDE cycle
The contents of CIR are split into operand and opcode
40
What occurs in the execute phase of an FDE cycle
The decoded instruction is executed
41
Where is data held for pipelining
In a buffer in close proximity to the CPU
42
Why are dual codes not useful
Not all programs are able to utilise multiple cores efficiently as they have not been designed to do so
43
Why are dual cores useful
Theoretically, they can complete tasks twice as fast as a single core.
44
Why is pipelining used on 3 separate instructions
While one instruction is being executed, another can be decoded, and another can be fetched
45
What is cache menory
The CPUs on board memory Instructions are fetched from main memory and are copied to the cache so that they can be accessed quicker As the cache fills up , unused Instructions are replaced
46
Properties of level 1 cache
Very fast memory cells (2 - 64 KB)
47
Properties of level 2 cache
Relatively fast memory cells (256 KB - 2MB)
48
Properties of level 3 cache
Much larger and slower memory cells
49
What is von neuman architecture
This architecture includes the basic components of the computer and processor (ALU , registers , memory units , control unit) In which a shared memory and shared data bus is used for both data and instructions
50
What is Havard architecture
This architecture has physically separate memories for instructions and data (This architecture is more commonly used for embedded processors)
51
Examples of havard architecture in use
This architecture is useful for when memories have different characteristics Instructions may be read only while data may be read and write
52
List some advantages of using von neuman architecture
It is cheaper to develop as the control unit is easier to design Programs can be optimised in size
53
List some advantages of havard architecture
Quicker execution as data and instructions can be fetched in parallel Memories can be different sizes, which can make more efficient use of space
54
What is contemporary processing
Processors which use a combination of hazard and von neuman architecture. Von neuman is used for working with data and instructions in main memory Havard is used to divide the cache into instruction cache and data cache

OCR A LEVEL Computer Science (1 decks)

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