Unit 1.1 - Systems Architecture Flashcards Preview

OCR GCSE 2019 COMPUTER SCIENCE > Unit 1.1 - Systems Architecture > Flashcards

Flashcards in Unit 1.1 - Systems Architecture Deck (26)
Loading flashcards...
1

Purpose Of The CPU

Continuously perform the
FDE cycle (Fetch, Decode, Execute)
Fetch Data & Instructions form Memory, Decodes and executes instructions

2

CU (Control Unit)

Controls the way data flows around the CPU

3

PC (Program Counter)

Stores the address of the data / instruction to be processed NEXT.

4

MAR (Memory Address Register)

Stores the address
of the data / instruction to be processed (Fetch/read)

5

MDR (Memory Data Register)

Stores the
data / instruction to be processed (fetch/read).

6

ALU (Arithmetic Logic Unit)

Performs Arithmetic Calculations & Logical Operations

7

ACC (Accumulator)

Stores the result of calculations by the ALU

8

IR (Instruction Register)

Stores instruction
currently being Processed

9

Registers

Temporary store of data on the CPU


(While the CPU performs the FDE Cycle it will
shift data in and out of the registers
such as the MAR, MDR, PC, ACC, IR)

10

Purpose of Cache

Stores frequently used
Instructions & Data

More Cache = More instructions & data stored less FDE Cycles used accessing main memory so programs run faster.

11

Clock Speed

The number of FDE cycles
the CPU can perform per second

Faster Clock speed = Faster FDE Cycles so more FDE cycles in a given time.

12

CPU Cores

Multiple CPUs
sharing the workload

More Cores = More FDE cycles can be completed in a given time.

Some tasks /software cannot be split/run across multiple cores.

13

An Embedded System

A computer system that is built into a product that performs a
dedicated function.

14

Embedded Systems - Features

1. Smaller than a PC.

2. No unnecessary features.

3. Usually automated.

4. Software stored in ROM needs firmware update to change.

15

Embedded Systems - Examples

Microwave,
Washing Machine,
Dishwasher,
Watch,
Sat Nav

16

Instruction Set

Set of commands
written in machine language
that the CPU understands

17

Opcode

Part of the instruction that tells the CPU What to do

18

Operand

Part of the instruction that is the Value or Memory location
(Where to do it)

19

Von Neumann Architecture

Instructions are fetched, decoded and executed one at a time.

Instructions and data are held together in the same memory space.


20

Fetch (FDE Cycle)

The CU sends the contents of the PC to the MAR
The CU then sends READ command on the Control Bus and Address of the data needed on the Address Bus.
The contents of Main Memory are sent via the data bus into the MDR.
The CU copies the data from the MDR to the IR
The PC is incremented so that it points to the next instruction to be executed.

21

Decode (FDE Cycle)

The CU decodes the instruction using an Instruction Set
The instruction is separated into the Opcode & Operand

22

Execute (FDE Cycle)

The function of the instruction is performed.
Move data to and from memory.
If the instruction involves arithmetic or logic, the ALU is utilized.
The ALU may utilize the ACC if it needs to store data to perform the calculation

23

BUS

Allow data to travel between the components, memory & other hardware.

24

Data Bus

Used to send the data / instructions needed from/to memory.


Bi-Directional
(both ways).

25

Control Bus

Used to send write to/read commands to components.

Bi-Directional
(both ways - can receive status signals from other components)

26

Address Bus

Used to send the Address of the data / instructions needed.

Uni-Directional
(one way only from the CPU to Memory)