Unit 2 Flashcards
What is Asynchronous Data Transfer and its methods?
Asynchronous Data Transfer
Used when devices (CPU & I/O) operate on different clocks.
1) Strobe Control
Single control line (strobe) used to signal data readiness.
Source-Initiated:
Source puts data on bus → sends strobe.
Destination reads data on strobe’s falling edge.
Destination-Initiated:
Destination sends strobe → Source puts data.
Destination reads and disables strobe.
❌ Disadvantage: No confirmation whether data was received or sent.
2) Handshaking (Two-wire control)
Solves strobe issues using 2 control signals.
Source-Initiated:
Source sends data + Data Valid.
Destination replies with Data Accepted.
Destination-Initiated:
Destination sends Ready for Data.
Source sends data + Data Valid.
Destination accepts and disables control.
✅ Advantage: Confirmation from both ends.
What is Serial Communication and its transmission modes?
1️⃣ Simplex
One-way communication
Example: Radio, TV
2️⃣ Half-Duplex
Two-way, but one direction at a time
Example: Walkie-talkie
3️⃣ Full-Duplex
Two-way, simultaneous
Example: Telephone
How does CPU communicate with IOP?
1️⃣ CPU sends Test I/O instruction to IOP.
2️⃣ IOP stores status word in memory.
3️⃣ CPU checks status from memory.
4️⃣ If OK, CPU sends Start I/O instruction.
5️⃣ IOP starts I/O program (via DMA).
6️⃣ CPU continues other tasks in parallel.
7️⃣ IOP finishes and sends Interrupt to CPU.
8️⃣ CPU sends Read I/O instruction.
9️⃣ IOP transfers final status word to memory.
🔟 Status shows success or error.
DMA Transfer
DMA Transfer (Direct Memory Access)
✅ Bypasses CPU for faster I/O.
Steps:
1️⃣ Peripheral sends DMA request → DMA raises BR (Bus Request).
2️⃣ CPU sends Bus Grant, releases control.
3️⃣ DMA sends DMA Acknowledge to peripheral.
4️⃣ RD/WR lines direction depends on BG (Bus Grant):
- BG = 0 → CPU ↔ DMA
- BG = 1 → DMA ↔ RAM
5️⃣ For each word:
- Address register incremented
- Word count decremented
6️⃣ DMA stops when count = 0 and removes bus request.
e modes of data transfer between CPU and I/O devices?
- Programmed I/O
CPU directly controls data transfer.
Needs constant monitoring of I/O device.
Slower & CPU is busy in loop until I/O is ready.
Example:
Input from device → Store in memory (via CPU)
- Interrupt-Initiated I/O
Uses interrupt signal to notify CPU when I/O is ready.
CPU can do other tasks until interrupted.
Two types:
Vectored Interrupt: Device sends address to jump to.
Non-vectored Interrupt: Uses fixed memory location.
Priority Interrupts: Decides which interrupt to handle first.
Daisy-Chaining: Serial connection; first device has highest priority.
Parallel Priority: Uses interrupt register, mask register, priority encoder.
- Direct Memory Access (DMA)
Fastest method.
CPU is not involved during data transfer.
DMA controller handles data transfer directly between memory and I/O.
Steps:
Peripheral sends DMA request (BR).
CPU sends Bus Grant (BG) → goes idle.
DMA uses buses → transfers data.
After transfer, DMA releases buses.
CPU resumes control.
Input–Output Interface
🔁 Why I/O Interface is Needed
Signal Conversion – Peripherals are electromechanical, CPU/memory are electrical.
Speed Mismatch – Peripherals are slower than CPU → Need synchronization.
Data Format Difference – Peripheral data format ≠ CPU format.
Different Operation Modes – Control is needed to avoid conflict between devices.
🔌 I/O Bus Interface Module
Bus lines: Data, Address, Control
Each peripheral has an interface unit.
CPU places the device address on the bus.
Interface activates if the address matches → Connects to the device.
Others stay disabled.
At the same time, CPU sends I/O command.
🛠️ Types of I/O Commands
Control Command – Activates device / tells what to do.
Status Command – Checks device/interface status.
Data Output Command – Sends data from CPU to device.
Data Input Command – Gets data from device to CPU.
🧩 I/O Interface Example
Registers:
Port A – Input port
Port B – Output port
Control Register – Set device operation
Status Register – Indicates device state
Bus Buffers – Use bidirectional bus for communication
Timing & Control Circuit – Detects bus address assigned
Example logic (using CS, RS1, RS2):
CS RS1 RS2 Register Selected
0 X X None
1 0 0 Port A
1 0 1 Port B
1 1 0 Control Register
1 1 1 Status Register
