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IC3 > VHDL > Flashcards

VHDL Flashcards

1
Q

Sintaxis librerías

A

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

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2
Q

Entity

A

entity nombre is
generic (cte1: tipo := valor1; cte2: tipo:= valor 2; …);
port (entrada1, entrada2, … : in tipo;
salida1, salida2, …: out tipo;
puertoi : modo tipo);
end entity nombre;

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3
Q

Entity

A

entity F is
generic (N: natural :=8);
port (A, B: in bit_vector(N-1 downto 0);
Y: out bit);
end F;

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4
Q

Architecture

A

architecture arch_name of entity_name is
– declaraciones de la arquitectura:
– tipos
– señales
– componentes
begin
– código de descripción
– instrucciones concurrentes
– ecuaciones booleanes
– componentes
process (lista de sensibilidad)
begin
– código de descripción
end process;
end arch_name;

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5
Q

Ejemplo de constante

A

constant DATA_WIDTH: integer := 8;

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6
Q

Ejemplo de signal

A

signal resultado: bit_vector(7 downto 0);

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7
Q

Ejemplo de variable

A

variable SIG1, SIG2: integer range 0 to 15;

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8
Q

Ejemplos de asignaciones

A

signal instrucc: bit_vector(15 downto 0);
alias c_op: bit_vector(3 downto 0) is instrucc(15 downto 12);
alias reg1: bit_vector(4 downto 0) is instrucc(11 downto 7);
alias reg2: bit_vector(4 downto 0) is instrucc(6 downto 2);

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9
Q

Ejemplos de asignaciones

A

signal CTRL: std_logic_vector(7 downto 0);
alias c_mux_8a1: std_logic_vector (2 downto 0) is CTRL(7
downto 5);
alias load_reg1: std_logic is CTRL(4);
alias load_reg2: std_logic is CTRL(3);
alias ALU_op: std_logic_vector(2 downto 0) is CTRL(2 downto
0);

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10
Q

Ejemplo de tipo

A

type color is (rojo, amarillo, azul);
signal BMP: color;
BMP <= rojo;

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11
Q

Ejemplo de tipo

A

type pal is array (0 to 15) of std_logic_vector (7 downto 0);
signal word: pal;
– word(integer/natural) <= vector de bits;
word(0) <= “00111110”;
word(1) <= “00011010”;
…
word(15) <= “11111110”;

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12
Q

Ejemplo de tipo

A

type matrix is array (0 to 15)(7 downto 0) of std_logic;
signal matriz: matrix;
matriz(2)(5)<=’1’;

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13
Q

Ejemplo de tipo

A

type conjunto is record
palabra: std_logic_vector (0 to 15);
valor: integer range -256 to 256;
end record;
signal dato: conjunto;
dato.valor <= 176;

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14
Q

Operadores

A

* +, -, , /, mod, rem** operaciones aritméticas
** +, - cambio de signo
* & concatenación
* and, or, nand, nor, xor operaciones lógicas
** := **asignación de valores a constantes y variables.
** <= **asignación de valores a señales.

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15
Q

Ejemplos de asignación

A

y <= (x and z) or d(0);
y(1)<= x and not z;
y <= x1&x2; – y=”x1x2”
c := 27 + r;

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16
Q

Conversión de tipos

A

Función Operando de entrada Operando de salida
to_bit() std_logic bit
to_stdulogic() bit std_logic
to_bitvector() std_logic_vector bit_vector
to_stdlogicvector bit_vector std_logic_vector

DUDOSO.A REVISAR.

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17
Q

Ejemplo de asignación

A

signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: bit_vector(3 downto 0);
a <= (b and to_stdlogicvector(c));

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18
Q

Estructura Básica de un Archivo fuente en
VHDL

A

architecture circuito of nombre is
– señales
begin
– sentencias concurrentes
process (lista de sensibilidad)
begin
– sentencias secuenciales
– sentencias condicionales
end process
end architecture circuito;

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19
Q

Secuencia concurrente WHEN – ELSE

A

señal_a_modificar <= valor_1 when condición_1 else
valor_2 when condición_2 else
…
valor_n when condición_n else
valor_por defecto;

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20
Q

Ejemplos when-else

A

C <= “00” when A = B else
“01” when A < B else
“10”;
———————————————
C <= “00” when A = B else
“01” when D = “00” else
“10”;

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21
Q

Secuencia concurrente WITH – SELECT – WHEN

A

with señal_condición select
señal_a_modificar <= valor_1 when valor_1_señal_condición,
valor_2 when valor_2_señal_condición,
…
valor_n when valor_n_señal_condición,
valor_por_defecto when others;

22
Q

Ejemplo with-select

A

with entrada select
salida <= “00” when “0001”,
“01” when “0010”,
“10” when “0100”,
“11” when others;

23
Q

Secuencia condicional IF – THEN – ELSE (obligatoriamente dentro de bloque process)

A

process (lista de sensibilidad)
begin
if condición then
– asignaciones
elsif otra_condición then
– asignaciones
else
– asignaciones
end if;
end process;

24
Q

Ejemplo if - then - else

A

process (control, A, B)
begin
if control = “00” then
resultado <= A + B;
elsif control = “11” then
resultado <= A – B;
else
resultado <= A;
end if;
end process;

25
Q

Secuencia condicional CASE – WHEN (obligatoriamente dentro de un bloque process)

A

process (lista de sensibilidad)
begin
case señal_condición is
when valor_condición_l =>
– asignaciones
…
when valor_condición_n =>
– asignaciones
when others =>
– asignaciones
end case;
end process;

26
Q

Ejemplo case - when

A

process (control, A, B)
begin
case control is
when “00” =>
resultado <= A+B;
when “11” =>
resultado <= A-B;
when others =>
resultado <= A;
end case;
end process;

27
Q

Secuencia condicional FOR - LOOP (obligatoriamente dentro de un bloque process)

A

process (lista de sensibilidad)
begin
for loop_var in range loop
– asignaciones
end loop;
end process;

28
Q

Ejemplo FOR - LOOP

A

process (A)
begin
for i in 0 to 7 loop
B(i+1) <= A(i);
end loop;
end process;

29
Q

Secuencia condiconal WHILE - LOOP (obligatoriamente dentro de un bloque process)

A

process (lista de sensibilidad)
begin
while condición loop
– asignaciones
end loop;
end process;

30
Q

Ejemplo WHILE - LOOP

A

process (A)
variable i: natural := 0;
begin
while i < 7 loop
B(i+1) <= A(i);
i := i+1;
end loop;
end process;

31
Q

Sentencia process

A

process (lista_de_sensibilidad)
– asignacion de variables
– opcional no recomendable
begin
– Sentenicas condicionales
– Asignaciones
end process;

32
Q

Descripción estructural

A

architecture circuito of nombre is
component subcircuito
port (…);
end component;
– señales
begin
chip_i: subcurcuito port map (…);
– Se puede combinar con la descripción
– behavioral (por comportamiento)
end circuito;

33
Q

Ejemplo de descripción estructural

A

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity F is
port (A, B: in std_logic;
Y: out std_logic);
end F;
architecture estructura of F is
component G
port (Ag, Bg: in std_logic; Yg: out std_logic);
end component;
component H
port (Ah, Bh: in std_logic; Yh: out std_logic);
end component;
component I
port (Ai, Bi: in std_logic; Yi: out std_logic);
end component;
signal YA, YB, Yout: std_logic;
begin
mod_G: G port map (A, B, YA);
mod_H: H port map (A, B, YB);
mod_I : I port map (YA; YB; Yout);
Y<=Yout;
end estructura;

34
Q

MULTIPLEXOR 2x1

A

entity mux2 is
port (D0, D1, S0: in std_logic; O out std_logic);
end mux2;

architecture behavioral1 of mux2 is
begin
O <= D1 when (S0 = ‘1’) else D0;
end behavioral1;

35
Q

MULTIPLEXOR 2X1 - ESTRUCTURAL

A

architecture structural of mux2 is
– declaración de componentes
component AND2
port (I0,I1: in std_logic; O: out std_logic);
end component;
component OR2
port (I0,I1: in std_logic; O: out std_logic);
end component;
component INV
port (I0: in std_logic; O: out std_logic);
end component;
– declaración de señales
signal S1,S2,S3: std_logic;
begin
U1: INV port map (S0,S1);
U2: AND2 port map (D0,S1,S2);
U3: AND2 port map (S0,D1,S3);
U4: OR2 port map (S2,S3,O);
end structural;

36
Q

WAIT

A

wait on lista_de_señales; No se ejecutan las instrucciones posteriores
hasta que no se modifique (a cualquier valor)
alguna de las señales de la lista.

wait for tiempo; No se ejecutan las instrucciones posteriores
hasta que no pase el tiempo indicado desde que
se llegó a la instrucción de wait.

wait until condicion; No se ejecutan las instrucciones posteriores
hasta que no se cumpla la condición.

37
Q

Ejemplo de wait

A

process
begin
B <= A;
wait until A = ‘1’;
C <= B;
end process

38
Q

Ejemplo de banco de pruebas

A

architecture testbench_arch of simulacion is
component circuito
port (entrada: in std_logic; …
salida: out std_logic);
end component;
– señales intermedias, mismos nombres y tipo que los
– de circuito
signal entrada: std_logic := ‘0’;
…
signal salida: std_logic;
– las señales out no se inicializan
begin
UUT : circuito port map (entrada, …, salida);
process
begin
wait for 200 ns;
entrada <= ‘1’;
…
—————————————-
wait for 100 ns; – Total: 300 ns
entrada <= ‘0’;
… -
—————————————
wait for T ns; – Total: 300 + T ns
entrada <= ‘1’;
…
—————————————-
wait for …
…
—————————————-
wait for 100 ns;
end process;
end testbench_arch;

39
Q

Ejemplo de reloj

A

process
begin
wait for 10 ns;
CLOCK_LOOP : loop
clk <= ‘0’;
wait for tiempo_en_baja ns;
clk <= ‘1’;
wait for tiempo_ en_alta ns;
end loop CLOCK_LOOP;
end process;

40
Q

Biestable tipo D sin reset

A

entity Biestable_D is
port(d, clk: in std_logic; q: out std_logic);
end Biestable_D;
architecture ARCH of Biestable_D is
begin
process (clk, d)
begin
if (clk’event and clk = ‘1’) then q <= d;
end if;
end process
end ARCH;

41
Q

Biestable de tipo D con reset asíncrono

A

entity Biestable_rD is
port(d, clk, reset: in std_logic; q: out std_logic);
end Biestable_rD;
architecture ARCH_ASYN of Biestable_rD is
begin
process (clk, reset, d)
begin
if (reset = ‘1’) then q <= ‘0’;
elsif clk = ‘1’ and clk’event then q <= d;
end if;
end process;
end ARCH_ASYN;

42
Q

Biestable de tipo D con reset síncrono

A

architecture ARCH_SYN of Biestable_rD is
begin
process (clk, reset, d)
begin
if clk = ‘1’ and clk’event then q <= d;
if (reset = ‘1’) then q <= ‘0’;
end if;
end if;
end process;
end ARCH_SYN;

43
Q

Ejemplo 1 reloj

A

process (clk, a, b, reset)
begin
if reset = ‘1’ then
b <= ‘0’;
c <= ‘0’;
elsif clk’event and clk =’1’ then
b <= a;
c <= b;
end if;
end process;

44
Q

Ejemplo 2 reloj

A

process (clk, a, b, reset)
begin
if reset = ‘1’ then
b <= ‘0’;
c <= ‘0’;
elsif clk’event and clk =’1’ then
c <= b;
b <= a;
end if;
end process;

45
Q

Ejemplo 3 reloj

A

process (clk, a, b, reset)
begin
if reset = ‘1’ then
b <= ‘0’;
c <= ‘0’;
elsif clk’event and clk =’1’ then
c <= a;
b <= a;
end if;
end process;

46
Q

Contador

A

entity contador is
port (reset, clk : in std_logic;
numero : out std_logic_vector(3 downto 0));
end contador;
architecture circuito of contador is
signal interna: std_logic_vector(3 downto 0);
begin
process (reset, clk, interna)
begin
if (reset = ‘1’)
interna <= “0000”;
elsif clk’event and clk = ‘1’ then
interna <= interna + 1;
end if;
end process;
numero <= interna;
end circuito;

47
Q

Contador genérico que cuenta hasta un valor máximo

A

entity contador is
generic (maximo: natural := max; N: natural := 8);
port (reset, clk : in std_logic;
numero: out std_logic_vector(N-1 downto 0));
end contador;
architecture circuito of contador is
signal interna: std_logic_vector(N-1 downto 0);
begin
process (reset, clk, interna)
begin
if (reset = ‘1’)
interna <= (others<=’0’);
– Esta sentencia pone todos los bits de interna a cero
elsif clk’event and clk = ‘1’ then
if interna < max
interna <= interna + 1;
else
interna <= (others=>‘0’);
– Esta sentencia pone todos los bits de interna a cero
end if;
end if;
end process;
numero <= interna;
end circuito;

48
Q

Registro de 8 bits

A

entity registro_8 is
port (clk, reset: in std_logic;
A: in std_logic _vector(7 downto 0);
B: out std_logic _vector(7 downto 0));
end registro_8;
architecture arch_reg of registro_8 is
begin
process(clk, reset)
begin
if reset=‘1’ then B<=“00000000”;
elsif (clk’event and clk=‘1’) then B<=A;
end if;
end process;
end arch_reg;

49
Q

Definición de estados

A

type ESTADOS is (S1, S2, S3, S4);
signal ESTADO, ESTADO_SIG: ESTADOS;

50
Q
A

IC3 (1 decks)

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