Week 5 Flashcards
What are the steps of the Fetch Decode Execute cycle?
Fetch - read an instruction from memory
Decode - identify the instruction
Execute - carry out the instruction
What is a Pipelined Cycle?
An ideal scenario, the rate of instruction execution is multiplied by the number of stages
What is Clock Cycle Time?
Time which each pipeline stage must complete its operation
What is Clock Speed?
Frequency at which the CPU’s clock runs (1/clock cycle time)
What is Execution Time (hint: … X … )?
Clock cycles for program x Clock cycle time
What are the 2 Pipeline Hazards?
Control Hazards
Data Hazards
What is a control hazard?
Occurs when a branch instruction changes the next instruction
What are the 3 ways to deal with control hazards?
- Stall the pipeline
- Assume branch not taken
- Branch prediction
What is Stalling the pipeline?
Stop fetching and executing next instructions until the branch result becomes known
What are the pros and cons of Stalling the pipeline?
Pros:
No need to do anything
Cons:
Wasting time and resources
What is Assuming the branch not taken?
The processor assumes branch not taken
Squashing instructions if wrong
What are the pros and cons of Assuming the branch not taken
Pros:
No need to guess the next instruction
Cons:
Wasting time and resources if branch taken
What is Branch Prediction?
The processor may try branch prediction based on past branches
If prediction is incorrect, instructions are squashed
What are the pros and cons of Branch Prediction?
Pros:
Can reduce wasted clock cycles
Cons:
Branch prediction overhead
What is a Data Hazard?
Occurs when an instruction requires a result from a previous instruction before that result has been computed/written
What are the types of Data Hazards?
Read after write (RAW) - True Dependency
Write after read (WAR) - Anti-dependency
Write after write (WAW) - Output dependency
What is Read After write (RAW) - True Dependency?
Instruction writes, then another reads same location
Hazard if read happens before write completes
What is Write After Read (WAR) - Anti-dependancy?
Instruction reads, followed by another writing to same location
Hazard if write completes before the read
What is Write After Write (WAW) - Output Dependancy?
Two instructions write to same location
Hazard if writes occur in reverse intended order
What are the side effects of Deeper Pipelines?
More pipeline stages means
A larger penalty for incorrect branch predictions
A bigger risk of data hazards
What is Caching?
A processor fetches instructions and data from cache memory if possible
What is Pipelining?
The execution of an instruction is divided into multiple stages
What is a Branch Prediction?
A processor predicts branches based on past history, and squashes instructions if wrong
What is Speculative Execution?
An optimization technique in which a processor (CPU) performs a series of tasks before it is prompted to, in order to have the information ready if it is required at any point
