Week 5 & 6 - CPU & Cache Flashcards

1
Q

``

What is CPU?

A

The central processing unit (CPU, or processor) is the part of the computer that executes program instructions on program data.

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2
Q

What is the ALU?

A

The ALU is a complex circuit that implements all arithmetic and logic operations on signed and unsigned integers.

The ALU takes integer operand values and an opcode value that specifies the operation to perform (e.g., addition). The ALU outputs the resulting value of performing the specified operation on the operand inputs and condition code values that encode information about the result of the operation.

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3
Q

Types of memory?

A

primary (stores data, programs, instructions) and secondary (external storage devices)

Primary is RAM (SRAM + DRAM) and ROM (PROM+EPROM+EEPROM)

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4
Q

Why is memory important?

A
  • Processing of large data (more memory, bigger capability for processing large data)
  • Operating Systems (lack of memory may increase chance of crashing or erroneous functioning)
  • Virtualization
  • Overall performance (more memory in the system provides better performance)
  • Browsing
  • Multitasking (running many applications simultaneously)
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5
Q

What does the line decoder do?

A

selects only one of the output lines to set to 1 for each input bit pattern
When Enable = 0, all the output lines are 0.
● When Enable = 1, the three-bit number at the input, x = x2x1x0, selects which output line is set to 1.

Input lines X Output lines
^ format of representing line decoders ^

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6
Q

How is storage spaace in a direct-mapped cache divided?

A

In cache lines.

Contains 2 types of information: cache data block and metadata.

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7
Q

Which part of the address identifies what line we are referring to?

A

index

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8
Q

What does the offset determine?

A

cache’s block size dimension, number of words

The offset portion of an address must contain enough bits to refer to every possible byte within a cache data block.

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9
Q

What does the number of index bits determine?

A

number of cache lines (or blocks)

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10
Q

Which type of caches suffer the most from conflicts?

direct-mapped, set associative, fully associative?

A

direct-mapped

For example, even if a direct-mapped cache is not 100% full, a program might end up with the addresses of two frequently used variables mapping to the same cache location. In such cases, each access to one of those variables evicts the other from the cache as they compete for the same cache line.

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11
Q

What’s a fully associative cache?

A

A fully associative cache allows any memory region to occupy any cache location. Fully associative caches offer the most flexibility, but they also have the highest lookup and eviction complexity because every location needs to be simultaneously considered during any operation.

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12
Q

What is set associative cache?

A

A set associative design offers a good compromise between complexity and conflicts. The number of lines in a set limits how many places a cache needs to check during a lookup, and multiple memory regions that map to the same set don’t trigger conflict misses unless the entire set fills.
In a set associative cache, the index portion of a memory address maps the address to one set of cache lines. When performing an address lookup, the cache simultaneously checks every line in the set.

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13
Q

Advantages and disadvantages of fully associative cache?

A

Pro: Flexible, data can be put anywhere (no conflicts)
Con: Have to search everywhere for data (slow/expensive)

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14
Q

Pros and cons of set-assocative cache?

A

Pro: reasonably flexible: data can be put anywhere in a set (reduced conflicts)
Con: have to search several places for data (reasonable speed/complexity)

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15
Q

Pros and cons of direct-mapped cache?

A

Pro: only have to search one location (fast/simple)
Con: Data can only be put in one location (conflicts)

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16
Q

Formula for miss ratio?

A

% of cache misses =
(#cache misses / # memory accesses)

17
Q

What is the average number of cycles for a memory access (AMAT)?

formula

A

(% hits) x (hit time) +(%miss) x (miss time + miss penalty)

miss = 1 - hits

hits - how well the cache works?
hit time - how fast is the cache?
miss time - time to figure out the data is not in the cache
miss penalty - time to get the data from DRAM

example:

hit time = 1
miss time = 1
miss penalty = 3

hit | miss | penalty | hit | hit | miss | penalty | hit

% miss = 2/6, % hits = 4/6

AMAT = (66%)x1 + (33%)x(1+3) = 2 cycles per access