X86-64 Divide Instruction

Question 1

When a 4 byte value is written to a 4 byte register, the upper 4bytes are set to _____

Answer 1

0

Question 2

%eax: 0x47372000
%edx: 0x00000757

We want 8-byte result: 0x000007574372000

Answer 2

Shlq $32, %rdx. //shift left 5 position
Orq %rdx, %rax //can also do addq

Question 3

What if multiply ushering imulw %cx giving us a 4 byte result where the lease significant 2bytes are %ax and most significant 2 bytes are %dx.

Answer 3

• GARBAGE can be in the upper 6 bytes in both register
• Must combine 2bytes values in %ax and %dx so we have a 4 byte value

Question 4

Mild for ________, doesn’t allow for use of more than one operant and always (_________) results in our 2w bit product being split between 2 registers. And we don’t have an option to compute a w-bit product

Answer 4

For unsigned values, except for 1-byte products

Question 5

If we are using imulX (for signed values) we have two other options

Answer 5

ImulX Sri, Dest
ImulX Imm, Src, Dest

But these options produce 2-bit results, so overflow is possible

Question 6

Imull %edx, %eax
Mule %dx

Answer 6

Full 4bytes result is in %eax
4-byte results is half of %dx and half of %ax

Question 7

What if we have 4-byte unsigned values

Answer 7

1. We could use mull %edx and have our 8-byte product split between %eax and %rdx
2. We could use imulY with two 8-byte operands: imulq %rdx, %rax

Now we have an 8 byte results for the 2nd option in %rax, no comtamination of %rdx register and knowledge tha there is not overflow

Question 8

What if we have two byte signed values??

Question 9

Two byte unsigned values
%ax contains multiple ant and %dx contains multiplier

Answer 9

1. Zero extend both register since upper bytes could have garbage and we know unsigned value
   Movzwl %ax, %eax
   Movzwl %dx, %edx
2. Use imulX with 2 4 byte operants
   Imull %edx, %eax

Question 10

2 byte signed value
%ax contains multiplicand, %dx contains multiplier

Answer 10

1. Signe extend from 2 bytes to 4 bytes because we know signed value
   Movswl %ax, %eax
   Movswl %dx, %edx
2. Use imull with 2 4-byte operants
   Imull %edx, %eax

Now we have 4 byte results in %eax, no contamination of %edx register

Question 11

Cltq

Answer 11

Sign extends %eax register to %rax
Short form of Movslq %eax, %rax

Question 12

Cqto

Answer 12

• Copies the sign bit of %rax to all the bits of %rdx

Question 13

128 bit division

Answer 13

1. ALU uses 2 8 byte register (%rax, %rdx)
2. Dividend is a only in %rax, must se %rdx to all 1’s or 0’s (sign or zero extend)
3. Either divq (unsigned) or idivq (signed) divide instruction is sued

Question 14

Suppose division and
%rdx (some address *qp)
%rax (x)

%rdx: 3rd parameter
%rax: 0xfffffffffffffffb (-5)

Answer 14

Cqto
%rdx = 0xffffffffffffffff %rax= 0xfffffffffffffffb
Idivq %rsi (divide by y)
%rdx = 0xffffffffffffffff (x %y)
%rax = 0cfffffffffffffffe (-2) -> (x/y)

Question 15

Unsigned division makes use of the _____ instruction. Typically, register %rdx is set to ____ beforehand rather than sign extending (using Cqto) and unsigned value because that can cause errors

Answer 15

Divq, 0

Question 16

When dividing signed 32-bit values (4 byte) the dividen
1) Must be placed in register _____
2) you must signe extend ____ to _____ (cltq will take care of this)
3) you must replicate the top half of ______ in _____. There are atleast 2 ways to do this, but it can be accomplished with Cqto

Answer 16

%eax
%eax, %rax
%rax, %edx