1.1.1 Structure And Function Of The Processor

Question 1

What is the CPUs function?

Answer 1

The CPU is responsible for processing all the data within the computer

Question 2

What are the components of the CPU?

Answer 2

The CPU consists of :
ALU
CU
Registers:
- PC
- MDR
- MAR
- ACC
- CIR

Question 3

What are (special) registers ?

Answer 3

-Small fast memory cells used for (temporarily) storing data, within the processor.
-They have faster access speeds than RAM/secondary storage.

Question 4

What is the Purpose of the ALU ?

Answer 4

Performs any arithmetical or logical operations.
E.g adding binary or using AND, OR, NOT

Question 5

What is the purpose of the CU ?

Answer 5

• Accepts the next instruction.
• decodes instructions [1]
• Sends control signals to coordinate the movement of data through the processor [1]

Question 6

Program counter (PC)

Answer 6

• Holds the address of the next instruction to be executed. [1]
• is incremented by 1 on every cycle [1]
• contents of the PC can be changed by BRANCH/JUMP instructions

Question 7

Accumulator (ACC)

Answer 7

• temporarily Stores the result of calculations ( usually from the ALU ) [2]
• holds all input/Output in processor [1]
• used as a buffer [1]
• checked for conditional branching [1]

Question 8

Memory address register (MAR)

Answer 8

• Hold the address of a location from which data/ instructions is to be fetched from of written to. [2]
• holds the address of the instruction sent from the PC [2]

Question 9

Memory data register (MDR)

Answer 9

• Temporarily stores data/instructions that has been read or data that needs to be written. [1]
• acts as a buffer [1]

Question 10

Current instruction register (CIR)

Answer 10

Holds the current instruction being executed divided up into operand and opcode

Question 11

Bi-directional

Answer 11

Bits can be carried in both directions

Question 12

What are BUSES?

Answer 12

• are a set of Parallel wires which connect 2 or more components inside the CPU.
• there are 3 buses which connect the CPU with the main memory (RAM) :
  The Data bus , address bus and control bus
• collectively known as the system bus

Question 13

Address bus

Answer 13

• Used to transmit memory addresses specifying where data is to be sent or retrieved from.
• adding a wire to the address bus doubles the number of addressable locations .

Question 14

Control bus

Answer 14

• this is a bi directional bus
• transmits control signals from the CU to other parts of the processor (to allow synchronisation of signals to the rest of the processor) [1]
• control signals include:
  Bus grants
  Bus requests
  Memory write
  Memory read
  Interrupt requests
  Clock

Question 15

Assembly language

Answer 15

• Assembly code uses mnemonics to represent instrucions e.g ADD represents addition
• it is a simplified way of representing machine code
• the instruction is divided up into operand and opcode

Question 16

Opcode

Answer 16

• is used to determine the type of instruction and what hardware to use to execute it
• is part of the instruction and indicates what to do and also contains the addressing mode

Question 17

Operand

Answer 17

• is the address of where the operation is performed

Question 18

FDE cycle

Answer 18

The sequence of operations that are completed in order to execute an instruction

Question 19

Fetch phase

Answer 19

1. PC is checked (as it holds the address of the next instruction to be executed )
2. Address from the PC is copied to the MAR
3. The address is sent along the address bus to main memory
4. CU sends a read signal down the control bus to main memory
5. Instructions stored at that address is sent down the data bus to the MDR
6. Instructions held in the MDR is copied to the CIR
7. Contents of the PC are incremented by 1

Question 20

Decode phase

Answer 20

• the CU decodes the instruction
• The contents of the CIR are split into operand and opcode

Question 21

Execute Phase

Answer 21

• operand is sent to/ stored in the MAR
• the address (operand) is sent down the address bus to main memory
• CU send a read signal down the control bus to the main memory
• contents stored at that address is sent down the data bus and stored in the MDR
• contents of the MDR are copied to the ACC

(Note: each line of LMC is one FDE cycle)
- The opcode is executed on the operand

Question 22

Factors affecting CPU performance

Answer 22

• Clock speed
• Number of cores
• Cache

Question 23

Clock speed

Answer 23

• the clock speed is the number of clock cycles completed in a seconds
• the higher the clock speed, The more clock cycles per second [1]
• so more instructions can be executed per second [1]
• therefore the program takes less time to run [1]

Question 24

Number of cores

Answer 24

• a core is an independent processor that is able to execute its own fetch-execute cycles
• a computer with multiple cores can complete more than one fetch-execute cycle simultaneously ( parallel processing )
• however some task can’t be spilt between cores and therefore have more cores is no quicker than having one
• some programs are not optimised for the use of multiple cores

Question 25

Cache

Answer 25

• is the CPUs onboard memory
• is part of primary storage and is used to store frequently used data and instructions
• the more cache there is, the more data can be stored for fast access by the CPU [1]
• if cache fills up, unused instructions get replaced

Question 26

Pipelining

Answer 26

• while one instruction is being fetched , another is being decoded and another is being executed [2]
• pipelining is the process of carrying out multiple instructions concurrently [1]
• the process off completing the fetch, decode and execute cycles of three separate instructions simultaneously

Question 27

Benefits of pipelining

Answer 27

• more instructions can be processed in the same amount of time [1]
• increasing the speed/performance of the program/ computer [1]
• the CPU is not idle while waiting for the next instruction
• (in the case of a branch, the pipeline is flushed , instructions currently in the pipeline are discarded/cleared)

Question 28

Von Neumann

Answer 28

• a computer design where both data and instructions share the same memory [1]
• same bus is used for both instructions and data [1]
• 1 instruction is processed at a time in a linear sequence using the FDE cycle [1]
• single control unit [1]
• used in most modern computers, microcontrollers

Question 29

Harvard architecture

Answer 29

• uses separate memory blocks/units for instructions and data [1]
• has separate buses for instructions and data (data and address) [1]
• is used in specialised embedded systems
• utilises pipelining
• has separate control units
• has fixed instruction size

Question 30

Von Neumann BENEFITS

Answer 30

• cheaper to develop since the control unit is easier to design
• programs can be optimised in size
• simple to design and implement

Question 31

HARVARD benefits

Answer 31

• quicker since data and instructions can be fetched in parallel
• both memories can be different sizes

Question 32

Contemporary processing

Answer 32

• the combination of Harvard and von Neumann architecture
• uses Von Neumann when working with data and instructions in main memory
• uses Harvard when working with cache ( there is an instruction cache and data cache )

Question 33

Data bus

Answer 33

Transfers data between components

Question 34

4 CASES during EXECUTE instructions

Answer 34

1) fetching/ getting DATA e.g. LDA - data goes from RAM to accumulator
2) writing data e.g. STA , data goes from ACC to RAM (value in the ACC is copied to MDR and value in the MDR is send down data bus to main memory . It is written to the given location
3) ALU related (add/sub)
4) BRA/BRZ/BRP PC is changed