Abbreviations Flashcards
(106 cards)
FOI
Freedom of Interference
FIT
Failure in Time (Hardware)
Depending on the type of component or system being evaluated, the FIT rate is one of the most commonly used metrics when calculating the level of reliability. It represents the failure rate (λ) per billion hours.
RTE>
Run Time Environment
FMEA
Fehler Möglichkeit Ereignis Analyse:
Is a team-oriented method to minimize risk during the development and is intended to promote the interdisciplinary cooperation of the involved parties at an early phase of the development cycle. It is designed to identify failures and measures to avoid them. In the nomenclature of the ISO 26262, the FMEA is an “inductive analysis method” (bottom up) for the “system design analysis”
ASIL
Automotive Safety Integrity Level
IF Set
Interface Set
SIL
Software in the Loop
PIE
Pre Integration Environment
SYS
System:
Final integration step of the zFAS software. Contains a zFAS platform and all SW components integrated.
EMS
Electronic Manufacturing Services
RTOS
Real Time Operating System:
Is an operating system (OS) intended to serve real-time applications that process data as it comes in, typically without buffering delays. Processing time requirements (including any OS delay) are measured in tenths of seconds or shorter increments of time. They either are event driven or time sharing. Event driven systems switch between tasks based on their priorities while time sharing systems switch the task based on clock interrupts.
GPU
Graphics Processing Unit
FPGA
Field Programmable Gate Array
Is an integrated circuit designed to be configured by a customer or a designer after manufacturing - hence “field programmable”. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an applications-specific integrated circuit (ASIC).
FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be “wired together”, like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
SAE
Society of Automotive Engineers:
The organisation had been founded in 1905 as Society of Automobile. Originally it supported standardisation in the automotive industry, to ensure the exchange of knowledge and ideas.
UTSP
Unshielded Twisted Single Pair:
Often grouped into sets of 25 pairs according to a standard 25-pair color code, made with copper wires measured at 22 or 24 and an insulator such as polyethylene or FEP and the total package covered in a polyethylene jacket.
AVB
Audio Video Bridging
TSN
Time Sensitive Networking:
VLAN
<p>Virtual Local Area Network:</p>
QoS
Quality of Service:
Latency
The delay of the end-to-end transfer
Jitter (Latency)
The deviation of the latency from its median value
Package Loss Rate (Latency)
The probability that single IP-Packages are lost during transmission (or arrive too late in real-time services)
RSTP
Rapid Spanning Tree Protocol:
BMCA
Best Master Clock Algorithm:
Allows a clock to automatically take over the duties of Grandmaster when the previous Grandmaster loses its GPS, gets disconnected due to a switch fault, or for whatever reason is unable to continue as Grandmaster.
Modulare Elektrifiyierungsbaukasten: Ist ein Baukastensystem für die Herstellung von Elektroautos, das VW derzeit entwickelt. Beim MEB werden in Zukunft die Anforderungen der Achsen, Antriebe, Radstände und Gewichtsverhältnisse hinsichtlich des e-mobility Trends ausgerichtet.