Computer Hardware Flashcards

(65 cards)

1
Q

CPUs and device _______ are connected through a common bus to a _______ memory

A

controllers, shared

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2
Q

What is a uniprocessor?

A

one processor with a single core

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3
Q

High _____ is important for a uniprocessor

A

frequency

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4
Q

Pre early 2000’s, ______ doubled in processors every 18 months

A

frequency

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5
Q

Post 2005, ______ ____ doubled in processors every 18 months

A

core count

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6
Q

What is a multicore processor?

A

one processor with multiple cores

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7
Q

A multicore processor contains both shared and core-private ______

A

caches

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8
Q

________ allows a core to execute more than one thread

A

hyper-threading

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9
Q

Multiple threads on one core still share caches, ______, etc

A

registers

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10
Q

Extra threads from hyper threading show up to the OS as additional _____ or ___

A

cores, CPUs

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11
Q

Mainstream servers using a multisocket motherboard usually have - sockets

A

2, 4

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12
Q

What does NUMA stand for?

A

Non-Uniform Memory Access

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13
Q

What is a NUMA node?

A

A processor and its local memory

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14
Q

Accessing _____ memory is faster than _____ memory in other NUMA nodes. This is known as the NUMA effect.

A

local, remote

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15
Q

An _________ is a communication medium that connect processors to processors or processors to memory in NUMA nodes

A

Interconnect

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16
Q

What does numactl do?

A

Control NUMA policy for processes or shared memory

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17
Q

What does htop do?

A

Interactive process viewer

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18
Q

What is Moore’s law?

A

the principle that the speed and capability of computers can be expected to double every two years, as a result of increases in the number of transistors a microchip can contain

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19
Q

Parallelism is offered by ______ ______ and ________

A

Hyper threading, Multi-core and multi-socket

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20
Q

What are the seven layers in the memory/storage hierarchy. (smallest to biggest)

A

Registers, L1, L2, L3, Main memory, Persistent memory, Flash/disk

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21
Q

The lower levels of the storage hierarchy contains the ______ of higher levels

A

contents

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22
Q

____, __, __, __ are examples of volatile SRAM

A

Registers, L1, L2, L3

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23
Q

Volatile DRAM is ______ memory

A

main

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24
Q

The _______ ______ points to the next instruction to execute

A

program counter

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25
Instructions and data moved between cache and memory in ______ ____ units
cache line
26
Describe the fetch, decode, execute cycle in a CPU
* Fetch next instruction: Instruction contains op-code and possibly data * Decode op-code * Execute op-code (using data if necessary)
27
Opcode instruction can include accessing data and moving between memory and _______
registers
28
______ are 100x faster than main memory
registers
29
What is the processor-memory gap?
CPU must bring data from memory to caches to registers
30
L1 and L2 caches are typically _______
core-local
31
___ cache is typically shared among all cores
L3
32
There are many more cache lines of memory than there are ____in the cache
slots
33
Cache lines are manage by a mapping function and _______ algorithm
replacement
34
What does DRAM stand for?
dynamic random access memory
35
What does it mean for memory to be volatile?
contents lost when power is out
36
____ is used to hold basic information like the BIOS
ROM
37
What is the basic building black of NAND flash memory?
floating gate transistors
38
In NAND flash memory, the cells are organized in _____ and _____
blocks, pages
39
In NAND flash memory, data can be written/read at the ____ level, while modifications must erase the _____
page, block
40
What is a disadvantage of NAND flash memory?
Cell wears out (dies) after a certain number of erases
41
How many threshold voltages does a multi-level cell for flash memory have?
3
42
SSDs imitate the same interface as _____
disks
43
The _____ ______ ______ (FTL) Maps flash blocks/pages to hard disk sectors using a mapping table
flash translation layer
44
The _____ inside SSDs caches data, the FTl mapping table, and sometimes the battery
RAM
45
Persistent memory is also known as _____ ______ ______ (NVM), ________ _____ ____ (NVRAM), or _______ ______ _____ (SCM)
Non-volatile memory, non-volatile RAM, storage class memory
46
Persistent memory as ____________ like DRAM and _________ like flash memory
byte-addressable, persistent
47
Persistent memory types include NVDIMM-_ (which is fast, small, and expensive), NVDIMM-_ (which is slow, large, cheap), and _______DC DIMM (which is balanced)
N, F, Optane
48
What does df do?
storage usage stats
49
what does mount do?
Mount existing file systems for access, or show | currently mounted file systems
50
What does iostat do?
Show storage I/O speeds
51
what does free do?
Show memory usage
52
Each device has its own _____
controller
53
Each device is managed by a device _______
driver
54
What does a device driver do?
* Software to use the controller * Provides a uniform interface to the device for OS * Specific to hardware and the OS using the device
55
Describe the process for reading a character from the keyboard
•CPU tells the keyboard controller “I need to read” •By loading registers in the device, using device driver •Keyboard controller knows “I got a read request” •By examining the registers •Keyboard receives a character and stores it in local buffer. Now the keyboard controller needs to let the CPU know that the operation is finished •This is done using interrupts
56
An ______ is a single sent by hardware devices to the CPU
interrupt
57
An ______ _______ ______ (ISR) (AKA interrupt handlers) stops the CPU from its current work to handle an interrupt
Interrupt service routine
58
After a CPU executes the ISR, it resumes its _______ job
previous
59
What is an Interrupt Vector?
A table indexed by device number whose entries contains address to the corresponding ISR
60
An I/O interrupt is sent when...
the read or write operation is completed or ended in an error
61
An timer expiry interrupt is sent when...
A regularly scheduled task beings or a task has exceeded its allocated time
62
An program generated interrupt is sent when...
an instruction causes a hardware error condition (ex divide by 0)
63
An Hardware failure interrupt is sent when...
hardware fails (ex parity error)
64
_____ _______ for interrupts is when the CPU waits for an I/O operation to finish before executing other jobs
Busy waiting
65
What is direct memory access for interrupts?
When a device transfers data from its local buffer directly into main memory.