CS401A's Pre-Finals: Comp. Sys. Architect Module 06 Flashcards
For pre-final and final exams. (69 cards)
1
Q
I/O Architecture
are the main vehicle for obtaining the benefits from the system
A
The peripheral devices
2
Q
I/O Architecture
since they are responsible for the input/output (I/O) and for connecting the system to the outside world.
A
The peripheral devices
3
Q
I/O Architecture
Some devices have a dual role, such as mass storage, networks, and so on—these are both
A
The peripheral devices
I/O devices.
4
Q
I/O Architecture
In general, these peripheral devices can be divided into the following:
A
- Input peripherals
- Output peripherals
- Input-output peripherals
- Storage
5
Q
I/O Architecture
— This allows user input from the outside world to the computer.
A
- Input peripherals
6
Q
I/O Architecture
— This allows information output from the computer to the outside world.
A
- Output peripherals
7
Q
I/O Architecture
— This allows information to be sent through input and output.
A
- Input-output peripherals
8
Q
I/O Architecture
— This allows the usage of I/O for storing and fetching of information.
A
- Storage
9
Q
I/O Architecture
I/O Characteristics
These are the following characteristics to consider in dealing with I/O devices and controllers:
A
- Computer usefulness ultimately depends on its I/O capabilities.
- I/O devices are incredibly diverse with respect to the following:
○ Behavior
○ Partner
○ Data rate - I/O considerations:
○ Performance
○ Expandability
○ Dependability
○ Cost
○ Size and Weight
10
Q
I/O Architecture
I/O Characteristics
* Computer usefulness ultimately depends on its
A
I/O capabilities.
11
Q
I/O Architecture
I/O Characteristics
* I/O devices are incredibly diverse with respect to the following:
A
○ Behavior
○ Partner
○ Data rate
12
Q
I/O Architecture
I/O Characteristics
* I/O considerations:
A
○ Performance
○ Expandability
○ Dependability
○ Cost
○ Size and Weight
13
Q
I/O Architecture
- I/O devices are incredibly diverse with respect to the following:
— input, output, or storage purposes
A
○ Behavior
14
Q
I/O Architecture
- I/O devices are incredibly diverse with respect to the following:
— human or machine interaction
A
○ Partner
15
Q
I/O Architecture
- I/O devices are incredibly diverse with respect to the following:
— the amount of data transferred to or from the I/O device in a period.
A
○ Data rate
16
Q
I/O Architecture
- I/O devices are incredibly divers with respect to the following:
It is typically measured in bits per second
A
○ Data rate
17
Q
I/O Architecture
- I/O considerations:
— This refers to how fast the device is.
A
○ Performance
18
Q
I/O Architecture
- I/O considerations:
— This refers to the expansion of the I/O device.
A
○ Expandability
19
Q
I/O Architecture
- I/O considerations:
— This refers to the capability of the range and control of an I/O device.
A
○ Dependability
20
Q
I/O Architecture
- I/O considerations:
— This refers to the cost (how cheap or expensive) of an I/O module or device.
A
○ Cost
21
Q
I/O Architecture
- I/O considerations:
— These refer to the dimensions of an I/O device.
A
○ Size and Weight
22
Q
I/O Architecture
Data Rate*
*Very Low <
A
500 bps;
23
Q
I/O Architecture
Data Rate*
Low <
A
5 Kbps;
24
Q
I/O Architecture
Data Rate*
Medium <
A
10 Mbps;
25
# **I/O Architecture**
**Data Rate***
**High**
10 — 100 Mbps;
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# **I/O Architecture**
**Data Rate***
**Very High**
100 — 5000 Mbps;
27
# **I/O Architecture**
**I/O Performance**
Below are the parameters used in checking the performance of each I/O device or controller.
* **I/O bandwidth (throughput)**
* **I/O response time (latency)**
28
# **I/O Architecture**
**I/O Performance**
— This is the amount of information that can be input (output) and communicated across an interconnect (say, for example, a bus) to the processor or memory (I/O device) per unit time.
* **I/O bandwidth (throughput)**
29
# **I/O Architecture**
**I/O Performance**
— This is the amount of information that can be input and communicated across an interconnect to the processor or memory per unit time.
○ How much data can be moved through the system at a certain time?
○ How many I/O operations can be done per unit time?
* **I/O bandwidth (throughput)**
30
# **I/O Architecture**
**I/O Performance**
— This is the total elapsed time to accomplish by an input or output operation.
* **I/O response time (latency)**
31
# **I/O Architecture**
**I/O Performance**
This is also an especially important performance metric in real-time systems.
* **I/O response time (latency)**
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# **I/O Architecture**
**Modes of I/O Data Transfer**
Data transfer between the central unit and I/O devices can be handled in three (3) types of modes:
* **Programmed I/O**
* **Interrupt Initiated I/O**
* **Direct Memory Access (DMA)**
33
# **I/O Architecture**
**Modes of I/O Data Transfer**
— These instructions are the result of I/O instructions written in a computer program.
* **Programmed I/O**
34
# **I/O Architecture**
**Modes of I/O Data Transfer**
The instruction in the program initiates each data item transfer. Usually, the program controls data transfer to and from the CPU and peripheral..
* **Programmed I/O**
35
**Modes of I/O Data Transfer**
Transfering data under programmed I/O requires constant monitoring of the peripherals by the CPU.
* **Programmed I/O**
36
**Modes of I/O Data Transfer**
The CPU has the following pair of registers to interface with an I/O device:
○ **WHAT** for holding I/O
○ **WHAT** for addressing the I/O device.
○ **Data register**
○ **Address register**
37
**Modes of I/O Data Transfer**
— The interface determines when the peripheral is ready for data transfer, then it generates an interrupt.
* **Interrupt Initiated I/O**
38
**Modes of I/O Data Transfer**
After receiving the interrupt signal, the CPU stops the task it processes and service the I/O transfer. Then, it returns to its previous processing task.
* **Interrupt Initiated I/O**
39
**Modes of I/O Data Transfer**
Interrupts require CPU immediate attention. These are the following uses of interrupts:
## Footnote
(e.g., keyboard input, power failure, completion of I/O, etc.)
○ **As an external event notifier.**
○ **As a completion signal.**
○ **As a means of allocating CPU time.**
○ **The interrupt as an abnormal event indicator.**
○ **Software interrupts.**
40
**Modes of I/O Data Transfer**
This process periodically checks for external events
## Footnote
(ex. checking keyboard input).
○ **As an external event notifier.**
41
**Modes of I/O Data Transfer**
It can be a notifier when a process is complete.
○ **As a completion signal.**
42
**Modes of I/O Data Transfer**
The time between interrupt pulses is known as a *WHAT*, which represents the time that each program or process will have alloted to it.
○ **As a means of allocating CPU time.**
*quantum*
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**Modes of I/O Data Transfer**
It uses traps or exceptions to avoid errors or illegal instructions.
○ **The interrupt as an abnormal event indicator.**
44
**Modes of I/O Data Transfer**
Programs or applications with higher priority and privileges can request a special interrupt if prompted.
## Footnote
(depending on the user's and system's grant)
○ **Software interrupts.**
45
**Modes of I/O Data Transfer**
— It is a technique of removing the CPU from the path and letting the peripheral device manage the memory buses directly to improve the speed of transfer.
* **Direct Memory Access (DMA)**
46
**Modes of I/O Data Transfer**
manages the transfer of data between peripherals and memory unit.
A **DMA (Direct Memory Access)** controller
47
**Modes of I/O Data Transfer**
Many hardware systems use WHAT, such as disk drive controllers, graphic cards, network cards, sound cards, etc.
* **Direct Memory Access (DMA)** DMA
48
**Modes of I/O Data Transfer**
In WHAT, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives a interrupt from the WHAT controller when the transfer has been completed.
* **Direct Memory Access (DMA)**
DMA
DMA
49
**Modes of I/O Data Transfer**
The three (3) main conditions to meet for a DMA to work are as follows:
○ Method to connect the I/O module and the memory
○ The I/O module must be able to read from and write to the memory
○ Method to avoid conflict between the CPU and the I/O module writing to memory at the same time.
50
**Modes of I/O Data Transfer**
There are different DMA methods of execution:
○ **Buffer Chaining**
○ **Operation Chaining**
51
**Modes of I/O Data Transfer**
■ It handles multiple transfers without the processor.
■ The device gives a linked list of buffers.
■ The device hardware uses the next buffer on the list automatically.
○ **Buffer Chaining**
52
**Modes of I/O Data Transfer**
■ Further optimization for smart device.
■ The processor gives a series of commands to the device, sometimes called a *WHAT WHAT*.
■ The device carries out successive commands automatically
○ **Operation Chaining**
*channel program*
53
serves as an intermediary interface between the CPU and a specific device that accepts commands from the CPU and controls the exact device after.
The **I/O Controller**
54
Most of the WHAT WHAT are device controllers that serve as direct interfaces between a general system bus and each of the system's peripheral devices.
**I/O Controller**s
55
In general, WHAT WHAT simplify the task of interfacing peripheral devices to a CPU.
**I/O Controller**s
56
offload a considerable amount of work from the CPU. They make it possible to control WHAT to a peripheral with a few simple WHAT commands from the CPU.
**I/O Controller**s
I/O
I/O
57
They also support DMA so the CPU may be free to perform other tasks.
**I/O Controller**s
58
provide the specialized circuitry required to interface different types of peripherals to the computer.
**I/O Controller**s
59
allow the processing of each instruction to progress in parallel.
**I/O Controller**s
60
**I/O Controller**
These are the following functions of an I/O controller:
* **Interface translation**
* **Addressing**
* **Multiplexing**
* **Buffering**
* **Error detection and correnction**
* **Control of multiple steps**
61
**I/O Controller**
— It includes the connection, voltage supply, protocol enactor, clocking.
* **Interface translation**
62
**I/O Controller**
— It is able to process memory locations or addresses for the function of processing.
* **Addressing**
63
**I/O Controller**
— It can combine multiple signals over the bus to reduce multiple bus usage.
* **Multiplexing**
64
**I/O Controller**
— It gives data transfer a boost by preloading data into memory before processing.
* **Buffering**
65
**I/O Controller**
— It can detect errors and correction.
* **Error detection and correnction**
66
**I/O Controller**
— This reduces CPU workload due to I/O controller being the one that processes I/O instructions.
* **Control of multiple steps**
67
**Computer Drivers**
is a small piece of software that tells the operation system and other software how to communicate with a piece of hardware.
A device driver
68
**Computer Drivers**
are like translators between a program being used and a device that program wants to utilize somehow.
Device drivers
69
**Computer Drivers**
In other words,
can provide information to a driver to explain what it wants a piece of hardware to do, information the WHAT WHAT understands and can fulfill with the hardware.
A software program
device driver
