ET VOL 6 CH 6,7 Flashcards
(200 cards)
1
Q
A
2
Q
Which of the following items is stored in main memory?
A
Data, programs, calculations, and operands
3
Q
Time interval from the instant a request for data is initiated until the data is available for use.
A
access time
4
Q
The output side of a flip-flop is read from memory without having to be rewritten
A
non-destructive readout
5
Q
The power to the computer is turned off and the contents of memory are retained.
A
nonvolatile memory
6
Q
The particular location of a larger memory array where a packet of information is located.
A
memory access
7
Q
Power is shut off to the computer and the contents of the semi- conductor memory are lost.
A
volatile memory
8
Q
The data is lost when it is read from memory.
A
destructive readout
9
Q
A memory unit that can receive requests from more than one CPU or I/O section is known as which of the following types of memories?
A
Multiported memory module
10
Q
Pcb type memories are usually composed of which of the following memory types?
A
Semiconductor
11
Q
In a typical square form memory, the intersection of an x row and y column is called a
A
memory word address
12
Q
The x rows and y columns of a typical memory will be equal in number.
A
true
13
Q
Memory operations in most computers usually include which of the following items?
A
- Control circuits 2. Timing circuits 3. Memory cycle
14
Q
Memory interface circuits include which of the following items?
A
Communication lines Interfacing register
15
Q
A word is read from memory, then rerouted back through the Z register to be rewritten. This is what type of memory?
A
Destructive readout
16
Q
Priority of memory requests are evaluated by which of the following devices?
A
Control circuits
17
Q
Memory read/write enables are provided by which of the following devices?
A
Timing circuits
18
Q
what is the memory cycle
A
read/write
19
Q
During a complete memory cycle, the first thing that must occur is which of the following?
A
Memory address translation is accomplished
20
Q
main memory is also called
A
ROM
21
Q
To locate a memory address word, the computer uses which of the following items in memory?
A
Memory logic
22
Q
The conversion from a logical to a physical memory address is a function of which of the following items in memory?
A
Memory logic
23
Q
In all computers, for every read operation there will always be a corresponding write operation.
A
false only in destructive memory
24
Q
In order to increase memory speed using interleaving, which of the following items are required?
A
More complex CPU and memory control circuitry
25
When odd parity is used for memory fault detection, all words stored in memory will have which of the following bits?
An odd number of set bits stored at each memory location
26
The memory protection register set is used for which of the following purposes?
To restrict read/write operations in portions of memory
27
In a memory segment within the protected area with all three bits of the memory protection control register set, which of the following operations are allowed?
1. Execute protected 2. Write protected 3. Read protected
28
Memory lockout is used by larger computers to prevent access to particular areas of memory by task state instructions. Which of the following describes the lockout function?
It is disabled when the CPU enters a particular executive or interrupt state and disabled when the CPU enters the task state
29
Compared with semiconductor memories, magnetic memories have which of the following advantages?
They require less power and they are nonvolatile
30
The state of a core or film is changed by which of the following conditions?
Current flow in the opposite direction of sufficient magnitude to overcome the magnetic field and to magnetize in the new direction
31
Compared with core memory, film memory has which of the following advantages?
Increased speed of read/write operations and less power required 2. More compact and durable 3. Twice as many memory cells can be put in the same space for the same amount of power
32
Each ferrite core can store what total number of bits?
1
33
In a four-wire core winding, what is the physical make up of the windings that are strung through each and every core?
2 drives lines, 1 sense line, and 1 inhibit line
34
What Detects the change in state of the core from one to zero.
Sense Line
35
What Each line provides 1/2 of the current necessary to change the state of the core.
Drive Line
36
What Prevents changing the core from a zero to a one.
Inhibit Line
37
In a three-wire core, this line performs the same function as in the four-wire core.
Sense
38
To simplify addressing, reading, and writing operations, magnetic cores are arranged in which of the following ways?
In matrices
39
Which core in an array will be switched from one state to another?
A core with a full read or write current passing through it
40
In a core array the inhibit line is threaded in (a) with the x or y drives (series, parallel) lines and the sense line threaded through (b) core. (each, every other)
(a) Parallel (b) each
41
What is the basic building block of the memory stack?
Memory Plane
42
The address register bits are used to translate the bits to make which of the following bit selections?
X and Y primary, secondary, and diode; stack; and inhibit upper and lower stack
43
Which selectors are activated only when writing zeros?
Inhibit
44
In a core read/write cycle, the read current is designed to change the state of the core(s) to (a) what value; and the write current is designed to change the state of the core(s) from (b) what value to (c) what value?
(a) Zero (b) zero (c) one
45
The process of reading cores to the zero state is known as which of the following types of readout?
Destructive readout
46
In a core memory, a restore cycle is necessary after data has been read from memory for what reason, if any?
To change the state of each selected core from zero to one
47
During a restore operation of zeros in a three-wire core, the absence of write current on which of the following lines will leave the cores in the zero state?
Digit
48
What specific number of paired film spots is used for each bit position?
Two
49
Current flow through which of the following lines will magnetize a film spot?
Word or sense/digit, depending on the function
50
In a film memory, a packet stores what specific number of bits of data?
2
51
Which, if any, of the following devices makes the mated film cells less susceptible to the disturbance from other cells in close proximity to them?
keeper (2nd film)
52
How is mated film memory structured?
Word organized
53
What item is the basic building block of the film memory stack?
packet (mated Film)
54
The memory capacity of a film core storage device is determined by which of the following factors?
Number of packets and the size of the array in the memory stack
55
In film storage, up to how many words can be selected at each memory location?
4
56
The address register bits used to translate the bits to make selections are processed in which of the following sequences?
Stack, memory location, and word at the address location
57
A mated film memory cell is read by which of the following methods?
A current is generated along the word line and a transverse field is applied to the thin film cell
58
What factor will determine the recorded state of the film?
The direction of the cell vector rotation induced film signal on the sense/digit line
59
When a one is to be stored, (a) what is the direction of the bit current in relationship to that used to store a zero and (b) what field steers the vector to the one state?
(a) Reversed (b) Longitudinal
60
In a restore operation of a film memory, what factor determines the direction of the digit current on the sense/digit line?
Binary value of the data register
61
Semiconductor memories are known by all of the following terms except which one?
Read-only memory (RAM)
62
Semiconductor memories have which of the following characteristics?
Non-destructive readout and volatile
63
Each RAM chip contains which of the following items?
Large numbers of memory cells and the logic to support them
64
The transistors used in flip-flops of static RAM may be MOS or bipolar. Compared to MOS, bipolar has what advantage, if any?
Higher access speed
65
In a static RAM, the address lines are used to enable the addressed memory cell flipflop circuit by row and column number.
true
66
Data is stored, or read from, the memory cells of SRAM via a total of how many lines?
4
67
The (a) address lines and the (b) I/O data lines are usually tied to what buses?
(A)Computer or memory system bus (B)Data bus
68
Each dynamic RAM cell consists of which of the following devices?
One MOS transistor and one tiny capacitor only
69
DRAM cells do not retain their charged state for more than a few milliseconds. This degradation is due to which of the following factors?
Time and temperature
70
To retain their charged state, DRAMs must be refreshed. Of the following methods, which one is (a) more cost effective because it uses what (b) device?
(A)External (B)Single refresh address generator
71
In DRAM organization, the data input and data output lines may be tied together in what type of application, if any?
One that uses a bidirectional data bus
72
Programs stored on ROM are often referred to as firmware for which of the following reasons?
They are more hardware than software
73
Compared to RAM, ROM has all of the same operational characteristics except which of the following?
Can be written to by normal computer accessing methods
74
ROM has what primary use?
Allows the computer to perform I/O operations
75
The acronym BIOS stands for what term?
Basic input/output system
76
The acronym NDRO stands for what term?
Non-destructive readout
77
In the example, the ROM chip memory array has a total of(a) how many decoders and (b) how many lines are input to these decoders?
(a) 2 (b) 13
78
ROMs may be made of which of the following materials?
Hardwired, magnetic, fusible links, and MOS and bipolar transistors
79
To perform ROM operations, which of the following circuits are used?
Timing, control signals, registers, flipflops, and internal buses
80
Compared to PROM, an erasable PROM has what additional advantage, if any?
It can be erased and reprogrammed
81
While still in the circuit, which of the following PROMS can (a) be programmed and (b) erased?
(a) EAPROM/EEPROM (b) EAPROM/EEPROM
82
A device that serves as a shared entry point from a local-area network into a larger information resource is which of the following?
Gateway
83
A function that transfers status by using the appropriate control signals from a transmitting device to the receiving computer is which of the following?
Input data (ID)
84
The I/O processor controls which of the following transfers?
The transfer of information between main memory and the external equipments
85
Establishing, directing, and monitoring transfers with external equipments are the functions of which of the following devices?
IOC input output controller
86
Changes to input and output control and data signal voltages are functions of which of the following devices?
IOA Input output adapter
87
The type of connectors for the I/O channels or ports will be dictated by which of the following factors?
Interfacing
88
The driver circuits are used for which of the following tasks?
To pass interface and data signals to the external equipments
89
Examples of consistencies found in the architecture of a computer’s I/O section include which of the following?
The arrangement and format of the information exchanged
90
If a printer senses a paper jam during a print operation, which of the following actions would occur?
A control word would be sent to the computer specifying an error condition (external interrupt)
91
Handshaking is also known by which of the following terms?
Function control word
92
The type of interface used when all bits of information represented by a byte or word are input or output simultaneously is known as which of the following formats?
Parallel format
93
Command instructions provide control over which of the following areas/operations?
IOC single and dual channel operations
94
The I/O command start instruction accomplishes which of the following actions?
Specifies an IOC, then halts further CPU processing
95
The CPU will delay processing while waiting for an I/O operation only during which of the following actions?
Executions of an I/O command start instruction
96
The actual execution of chaining instructions is independent of the CPU.
true
97
Input and output chains deal primarily with which of the following activities?
Transfer of blocks of information
98
Data transfer between the computer and external equipments will take place when which of the following conditions is/are met?
Initiate input/output or equivalent instruction is executed by the CPU
99
Which of the following is one of the constants in all I/O operations?
When the data transfer will begin
100
In I/O operations, communications with the external equipment require which of the following devices/operating modes?
A single channel operating mode
101
When an index address in main memory is specified by an external equipment during an I/O operation, the computer is operating in which of the following modes?
Externally specified index mode (ESI)
102
In I/O operations, which of the following is one of the primary uses of registers?
To enable and route both control and data information, CPU I/O and memory
103
Decoder circuits are used for which of the following purposes?
Address translation
104
Status registers are used for which of the following purposes?
To hold information for the CPU that indicates the operating condition and current activities of the external equipments
105
In computers with an IOC, once started the master clock can be stopped when which of the following actions occurs?
Computer master clear
106
In computers with an IOC, the master clock is started when which of the following actions occurs?
1. The computer is initially powered on 2. The computer is auto restarted
107
The I/O control circuits are controlled by which of the following means?
the computer program
108
A sequential set of memory locations that contains data to be sent out or an area that is set aside for data to be received is called which of the following?
A buffer
109
Which of the following are unbuffered operations?
CPU and various parts of the computer
110
The I/O processor’s sequencing circuits control which of the following actions?
The order in which events will be executed based upon the translated function code
111
The CPU interfaces with the I/O processor through which of the following means?
The CPU’s I/O instructions
112
I/O control memory words are set aside in main memory to control which of the following actions?
Data transfers for I/O buffer functions
113
In parallel operations, each I/O channel has its own block of memory addresses for which of the following operations?
Input, output, external function, and external interrupt operations
114
Serial operations are affected by which of the following factors?
Character size, parity selection, baud rate, and synchronous and asynchronous interfacing
115
Monitor words are used for which of the following purposes?
To store characters for comparison with received data characters
116
Another term for accumulator based I/O is which of the following?
Direct CPU interface
117
The CPU handles all I/O transactions by executing one or more instructions for each word of information transferred. This process is known by which of the following terms?
Accumulator based I/O (direct CPU interface
118
In memory mapped I/O, the CPU accesses the I/O device by which of the following means?
Placing appropriate addressing information on the bus
119
The main advantage of direct memory access is which of the following?
speed
120
When the CPU and the DMA attempt to access main memory simultaneously, the CPU has priority.
false DMA (direct memory access)
121
When a high speed disk drive is used, output data will be in which of the following forms?
Binary
122
The technique used when more than one peripheral device is connected to a single port/channel is known by which of the following terms?
Daisy chaining
123
When more than one peripheral device is connected to a single port/channel, the priority of a device is determined by which of the following factors?
CPU
124
When using a request and acknowledge system, the priority of the fictions and channels is determined by which of the following factors?
The I/O controller
125
Communication formats are governed by which of the following items?
The interfacing standard
126
The compatibility of voltage levels between the computer and external equipments is ensured by which of the following means
The I/O processor
127
Transfer of data within a digital computer is accomplished internally using which of the following means?
Parallel format
128
The conversion of data for transmission over a serial channel is accomplished by which of the following means?
A universal receiver-transmitter
129
When a universal synchronousasynchronous receiver transmitter is used, it functions as which of the following devices?
A peripheral device to the microprocessor
130
The universal synchronous-asynchronous receiver transmitter’s specific asynchronous interfacing is controlled by which of the following means?
The CPU
131
The read/write control logic accepts control signals from which of the following devices?
2. The control bus
132
To program the USART for the applicable interface when it is in an idle state, which of the following signals/words is required?
4. A new set of control words
133
The universal synchronous-asynchronous receiver transmitter is enabled for reading/writing operations when which of the following signals is true?
2. The CHIP SELECT
134
When the WRITE DATA (WD) signal is true, it means which of the following things?
It indicates the microprocessor is placing data on the data bus
135
When the READ DATA (RD) signal is true, the microprocessor is ready for which of the following activities?
3. To receive data and status words
136
The transmit control logic converts the data bytes stored in the transmit buffer into which of the following forms?
1. An asynchronous bit stream
137
A start bit is used for which of the following purposes?
2. To alert the output device
138
A parity bit is used for which of the following purposes?
3. To detect errors
139
The receive buffer stores which of the following information?
4. Parallel bytes
140
The voltage and current characteristics of line drivers/receivers are dictated by which of the following factors?
Type of circuitry (TTL or MOS
141
Type A (NTDS) Slow interface format is able to transmit which of the following number of bit groupings?
16, 30, or 32, depending on the type of computer
142
The data transmission rate for Type A (NTDS) Slow format is limited by which of the following factors?
The large voltage change between logic states
143
In Type D (NTDS SERIAL) interface format, information frames are made up of what total number of bits?
32 bits
144
Type D (NTDS SERIAL) interface format can transmit digital signals up to which of the following lengths?
1000ft
145
Type E (NATO SERIAL) format requires which of the following I/O cables?
Triaxial
146
Type E (NATO SERIAL) format is most frequently used with which of the following equipment?
Mainframe computers
147
Type F (aircraft internal time division multiplex [TDM] bus) interface format transmits bit groupings consisting of what total number of bits?
20
148
Type F (aircraft internal time division multiplex [TDM] bus) interface format can handle which of the following numbers of external devices on one channel?
32 (including a bus controller
149
Type G (RS-449) interface format primarily uses which of the following protocols?
2. Command and response
150
The Small Computer System Interface (ANSI X3.131) using one controller can daisy chain up to what maximum number of units?
8
151
The RS-232 interface can be used for which of the following types of transfers?
4. Asynchronous and synchronous serial
152
The RS-232 interface can be used with which of the following types of computers?
4. Micros, minis, and mainframes
153
The RS-232 interface limits cable transfers to what maximum number of feet?
50ft
154
In the RS-232 interface, most peripherals control configuration parameters using which of the following methods?
dip switches
155
The higher transmission rate of the RS-422 interface is made possible by which of the following techniques?
1. Two separate wires are used 2. The receiver transition period is narrower 3. The grounding requirements are less critical
156
In a token ring network, a station with a message waits until it receives a free token, it then changes the free token to a busy token, and transmits a block of data following the busy token. What term is used for the block of data?
frame
157
The Ethernet interface is used to transfer which of the following types of data in what format?
1. Serial I/O data in packet format
158
The type of cable used for the Ethernet interface is which of the following?
3. Shielded coaxial
159
Thin Ethernet interface used in smaller systems can have a maximum cable length of which of the following?
1000ft
160
The Centronics Compatible Parallel interface uses which of the following types of protocol?
1. Command/acknowledge
161
Most floppy disk drives today are controlled by which of the following interfaces?
2. ST-506/412 interface
162
When using the ST-506/412 interface, the controller card performs which of the following functions for disk drives?
1. Moves the magnetic head 2. Spins the magnetic disk 3. Strips off formatting and control words
163
When using the ST-506/412 to interface a hard disk drive, the cabling required is which of the following?
1. A 34-pin control cable 2. A 20-pin data cable
164
When using the ST-506/412 to interface a floppy disk drive, the cabling required is which of the following?
34-pin control cable
165
The enhanced small device interface can transfer data at up to which of the following rates?
24 megabits per second
166
When using the enhanced small device interface with a floppy disk drive, the cabling required is which of the following?
1. A 34-pin control cable 2. A 20-pin data cable
167
All electronics used for the integrated drive electronics interface are located in which of the following areas?
The hard drive
168
The integrated drive electronics interface can handle disk drives with a maximum capacity of which of the following?
300 MB
169
The minimum number of conductors required for I/O serial data operations is which of the following?
4
170
During asynchronous data exchange, a frame of data must include which of the following bits at a minimum?
1. One start bit 2. One stop bit 3. Seven character bits
171
During asynchronous data exchange, the maximum number of bits for one frame of data is which of the following?
11
172
Compared to asynchronous data exchange, synchronous data exchange has which of the following advantages?
Faster speed
173
The generally accepted standard connector for implementing an RS-232 connection has what total number of pins?
25
174
The protective ground, pin 1 of the RS-232 interface connector in the DTE/DCE mode should always be connected to the shielded cable shield at both ends.
false just one side
175
Pin 7 of the RS-232 interface connector in the DTE/DCE mode should always be connected at both ends for which of the following reasons?
To complete the path for control signals only
176
Pin 3 of the RS-232 interface connector in the DTE/DCE mode is used for which of the following purposes?
To receive data signals
177
Pins 4, 5, 6, and 20 are used in the DTE/DCE mode using the RS-232 interface connector for which of the following purposes?
To establish the communications link (pin 4-send)(pin 5 clear to send)(pin-6 data ready set)(pin 20 data terminal reads)
178
In parallel data operations, the IOA or line driver/receiver provides the means to accomplish which of the following tasks?
2. Drive or detect the digital signals
179
In parallel data operations, one I/O channel could consist of which of the following devices?
1. Two cables, one for input and one for output or a single cable to handle both input and output 2. Eight or more data lines 3. A number of control lines
180
The data strobe in single parallel cable operations is used for which of the following purposes?
Signals the external device that data is ready to be read from the data lines
181
In single parallel cable operations, a busy signal would be sent under which of the following conditions?
The external equipment input buffer is full
182
In two cable parallel operations, an external interrupt enable can be described as which of the following?
A signal sent from the computer on the input line
183
When an external interrupt code is placed on the data lines, it is accompanied by which of the following signals?
1. An external interrupt request
184
In a two cable sequence of events for input data, the first event will be which of the following?
The external equipment places a word of data on the ID lines
185
In the two cable sequence of events for input data, the computer has sampled the data on the ID lines. Which of the following events must occur before the computer will accept more data?
1. The IDR must be cleared
186
During a normal external function sequence of events, the computer places an EF code word on the OD lines. The next event to take place is which of the following?
1. The EFR line is set External Fuction Ready
187
During forced external functions, the computer does not require which of the following signals?
EFR External Fuction Ready
188
During the external interrupt sequence of events, what is the first event that must occur before a computer will accept an external interrupt?
The EIE line is set
189
All computers used by the Navy will have EIE lines.
false
190
In intercomputer I/O operations when parallel channels are used, the input and output cables will have which of the following characteristics?
The input and output cables will be identical
191
During intercomputer I/O operations, command words include which of the following data?
External functions, forced external functions, and external function buffer words
192
During intercomputer I/O operations, command word functions are identified by use of which of the following techniques?
3. Additional interface signals
193
For an intercomputer command word buffered transfer, the receiving computer is ready to accept an external function command word. This is signaled by which of the following means?
The external interrupt enable line is set
194
During an intercomputer command word buffered transfer, before putting the EF code on the data lines, the transmitting computer recognizes which of the following signals?
EFR External Function Ready
195
In intercomputer I/O operations, all command words specified by the receiving computer’s EF buffer control words will be transferred one command word at a time.
true
196
Before the intercomputer data transfer sequence of events can begin, which of the following events must have occurred on the same channel?
1. An OD buffer must have been established on the transmitting computer 2. An ID buffer must have been established on the receiving computer
197
In intercomputer data transfers, the data word is held on the OD lines until the receiving computer performs which of the following tasks?
3. Sets the resume line
198
In intercomputer data transfer, the receiving computer recognizes the ready line of the transmitting computer as what line?
1. The IDR line
199
In intercomputer data transfer, the transmitting computer recognizes the IDA line of the receiving computer as what line?
The resume line
200
In intercomputer data transfer, after one data word has been transferred and before the next data word is placed on the data OD lines, which of the following events occurs?
1. The receiving computer sets the IDA line 2. The transmitting computer clears the ready line
