exercises

Question 1

A program runs in 12 seconds on computer A, which has a 3 GHz clock. We want to design computer B to run the same program in 8 seconds. However, computer B will require 15% more CPU cycles than computer A to execute the program.
* a. What is the number of CPU cycles on computer A?
* b. What is the required clock rate for computer B in GHz?

Question 2

A benchmark program is run on a 50 MHz processor. The executed program consists of 200,000 instruction executions, with the following instruction mix and clock cycle count:
* Integer Arithmetic: 80,000 instructions, 1 cycle/instruction
* Data Transfer: 60,000 instructions, 2 cycles/instruction
* Floating Point: 40,000 instructions, 3 cycles/instruction
* Control Transfer: 20,000 instructions, 2 cycles/instruction
Determine:
* a. The effective CPI (Cycles Per Instruction).
* b. The MIPS (Millions of Instructions Per Second) rate.
* c. The execution time for this program.

Question 3

Assume a pipeline with four stages: Fetch Instruction (FI), Decode Instruction & Fetch Operands (DI), Execute Instruction (EI), and Write Back (WB).
Draw a timing diagram (similar to Figure 14.10 or Problem 1 solution in your assignment) for a sequence of 7 instructions. Assume the third instruction is a conditional branch to instruction 7, and the branch is taken. There are no data dependencies. Show how the pipeline behaves.

Question 4

Given the following memory values and a one-address machine with an accumulator:
* Memory location 50 contains the value 80.
* Memory location 60 contains the value 90.
* Memory location 70 contains the value 50.
* Memory location 80 contains the value 70.
* Memory location 90 contains the value 60.
What value is loaded into the accumulator by the instruction “LOAD INDIRECT 70”?

Question 5

Compare zero-, one-, two-, and three-address machines by writing programs to compute:
Y = (R * S - T) / (U + V * W)
Use the same instruction set format provided in your Assignment 2, Problem 3 (PUSH, POP, LOAD, STORE, ADD, SUB, MUL, DIV for 0/1 address; MOVE, ADD, SUB, MUL, DIV for 2/3 address). List the instructions for each of the four machine types. You may use temporary memory locations (e.g., T1, T2) or register names as appropriate for the address type.

Question 6

A pipelined processor has a clock rate of 3.0 GHz and executes a program with 2.0 million instructions. The pipeline has six stages, and instructions are ideally issued at a rate of one per clock cycle. Ignore penalties due to branch instructions and out-of-sequence executions for speedup calculation. Assume CPI is 1 for throughput.
* a. What is the ideal speedup of this processor for this program compared to a non-pipelined processor?
* b. What is the throughput (in MIPS) of the pipelined processor?

Question 7

A main memory consists of 32768 blocks. The block size is 32 words, and each word is 2 bytes. A direct-mapped cache associated with this memory contains 32 lines. The main memory is addressable by byte.
* a. What is the size of the main memory in bytes?
* b. What is the length of the main memory address in bits?
* c. What is the size of the tag field in each memory address for the direct-mapped cache?
* d. How is the main memory byte address divided (into tag, line, and word/byte offset bits) for this direct-mapped cache? Specify the number of bits for each field.