lesson 7 Flashcards

(20 cards)

1
Q

: What is the primary function of the ALU in a processor?

  • A) Fetch instructions from memory
  • B) Decode instructions
  • C) Perform arithmetic and logical operations
  • D) Control the flow of data
A

C) Perform arithmetic and logical operations

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2
Q

Question: Which of the following is NOT a stage in a typical instruction execution cycle?

  • A) Fetch
  • B) Decode
  • C) Compile
  • D) Execute
A

C) Compile

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3
Q

: What is pipelining in processor design?

  • A) A technique to increase clock frequency
  • B) A technique to execute multiple instructions simultaneously
  • C) A technique to reduce power consumption
  • D) A technique to increase cache size
A

A technique to execute multiple instructions simultaneously

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4
Q

What type of hazard occurs when an instruction depends on the result of a previous instruction still in the pipeline?

  • A) Structural hazard
  • B) Data hazard
  • C) Control hazard
  • D) Memory hazard
A

B) Data hazard

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5
Q

Which register holds the address of the next instruction to be fetched?

  • A) Accumulator
  • B) Program Counter
  • C) Memory Address Register
  • D) Instruction Register
A

B) Program Counter

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6
Q

: What is a superscalar processor?

  • A) A processor that can execute more than one instruction per clock cycle
  • B) A processor with a very high clock frequency
  • C) A processor with a very large cache
  • D) A processor with multiple cores
A

A processor that can execute more than one instruction per clock cycle

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7
Q

Which of the following is a control hazard in pipelining?

  • A) Two instructions need the same functional unit
  • B) An instruction depends on data from a previous instruction
  • C) A branch instruction changes the program flow
  • D) Cache miss delays instruction fetch
A

C) A branch instruction changes the program flow

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8
Q

What is the purpose of branch prediction in modern processors?

  • A) To reduce power consumption
  • B) To reduce control hazards in the pipeline
  • C) To increase cache hit rate
  • D) To improve memory access time
A

B) To reduce control hazards in the pipeline

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9
Q

Which of the following is NOT a common register in a typical processor?

  • A) Program Counter
  • B) Stack Pointer
  • C) Memory Buffer Register
  • D) Graphics Processing Register
A

D) Graphics Processing Register

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10
Q

What is the function of the control unit in a processor?

- A) Perform arithmetic operations
- B) Store data temporarily
- C) Generate control signals for instruction execution
- D) Interface with external devices
A

C) Generate control signals for instruction execution

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11
Q

: What is a structural hazard in pipelining?

- A) When two instructions need the same hardware resource
- B) When an instruction depends on the result of a previous instruction
- C) When a branch instruction changes the program flow
- D) When cache misses delay instruction execution
A

A) When two instructions need the same hardware resource

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12
Q

Which technique is used to handle data hazards in pipelining?

- A) Branch prediction
- B) Forwarding (bypassing)
- C) Out-of-order execution
- D) All of the above
A

B) Forwarding (bypassing)

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13
Q

: What is the purpose of the Instruction Register (IR)?

- A) To hold the address of the current instruction
- B) To hold the current instruction being executed
- C) To hold the result of the ALU operation
- D) To hold the address of the next instruction
A

B) To hold the current instruction being executed

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14
Q

: Which of the following best describes a VLIW (Very Long Instruction Word) architecture?

- A) Instructions with variable length encoding
- B) Multiple operations packed into a single instruction
- C) Instructions that operate on vector data
- D) Instructions with very complex addressing modes
A

B) Multiple operations packed into a single instruction

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15
Q

: What is the primary advantage of a hardwired control unit over a microprogrammed control unit?

- A) Easier to design
- B) More flexible
- C) Faster execution
- D) Lower power consumption
A

: C) Faster execution

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16
Q

: What is instruction-level parallelism?

- A) Executing multiple programs simultaneously
- B) Executing multiple threads of a program simultaneously
- C) Executing multiple instructions of a program simultaneously
- D) Executing multiple processes simultaneously
A

C) Executing multiple instructions of a program simultaneously

17
Q

Which of the following is NOT a technique used in modern processors to improve performance?

- A) Branch prediction
- B) Out-of-order execution
- C) Register renaming
- D) Increasing the number of pipeline stages indefinitely
A

D) Increasing the number of pipeline stages indefinitely

18
Q

What is the purpose of the Memory Address Register (MAR)?

- A) To hold the data to be written to memory
- B) To hold the address of the memory location to be accessed
- C) To hold the data read from memory
- D) To hold the current instruction being executed
A

: B) To hold the address of the memory location to be accessed

19
Q

: What is speculative execution?

- A) Executing instructions before knowing if they will be needed
- B) Executing instructions in a random order
- C) Executing instructions only when all dependencies are resolved
- D) Executing instructions based on user preferences
A

A) Executing instructions before knowing if they will be needed

20
Q

: Which of the following is a characteristic of a RISC processor?

- A) Complex instruction set
- B) Variable instruction length
- C) Load/store architecture
- D) Microprogrammed control unit
A

C) Load/store architecture