export_week 8 instruction set architectures

Question 1

,

Instruction Set Architectures, what do it do?

Answer 1

ISA

ISA determines instruction formats

Question 2

,

– The LMC is a

Answer 2

one-address architecture (an accumulator-based machine).–

e.g., the instruction ADD X

Question 3

,

other instructions set and why

Answer 3

There are other instruction set architectures, all based on the number of

explicit operands .

0-address (stack)

1-address (accumulator)

2-address

3-addres

Question 4

,

0-Address Machines

Answer 4

– All operands for binary operations are implicit on the stack. Only push/pop

reference memory.

– e.g., calculating

a = a * b + c – d * e

Question 5

,

1-Address Machines

Answer 5

Accumulator is a source and

destination. Second source is

explicit.

Question 6

,

1-Address Machines

Answer 6

10 memory

references, not

including

instruction fetch

Question 7

,

2-Address Machines

Answer 7

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_245-14A61F370A37A2BD282.png

Question 8

,

2-Address Machines

Answer 8

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_246-14A61F45B74229CEDAE.png

Question 9

,

2-Address Machines with registers ?

Answer 9

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_247-14A61F50C171EEB8E26.png

Question 10

,

3-Address Machines

Answer 10

– One destination operand,

two source operands,

all explicit

Question 11

,

3-Address Machines eg without registers ?

Answer 11

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_248-14A61F622D5078C6512.png

Question 12

,

3-Address Machines without registers?

Answer 12

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_249-14A61F7191F1FB1AE34.png

Question 13

,

6 memory accesses;

general purpose

registers make a

substantial

difference.

Answer 13

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_250-14A61F8185A11F9B07D.png

Question 14

,

Comparison

– Assume 8 registers (3 bits),

• 32 op-codes (5 bits), 15-bit addresses,
• 16-bit integers.

– Which ISA accesses memory the least?

Answer 14

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_251-14A61F9BCDF25EF0299.png

Question 15

,

0-address

Answer 15

(stack)

Question 16

,

1-address

Answer 16

(accumulator)

Question 17

,

2-address

Answer 17

(register variant is 11⁄2-address)

Question 18

,

3-address

Answer 18

(with register variant

Question 19

,

The instruction set architecture determines

Answer 19

the format of instructions (and

therefore the assembly language).

Question 20

,

Four basic types with variations:?

Answer 20

1. 0-address (stack)
2. 1-address (accumulator)
3. 2-address (register variant is 11⁄2-address)
4. 3-address (with register variant

Question 21

,

ISA dramatically affects what ?

Answer 21

the number of times memory is accessed.

Question 22

,

CISC

Answer 22

Complex Instruction Set Computers

Question 23

,

RISC

Answer 23

Reduced Instruction Set Computers

Question 24

,

Motivation for CISC

Answer 24

Early computers had very little and very slow memory. Thus, the fewer instructions fetched, the faster the computer could be.

Question 25

# , General characteristics: CISC

Answer 25

High number of operations (300+) Compilers have less work to do to translate HLL into machine code. Large number of instruction formats Multi-clock cycle instructions Fewer registers; more memory access Large number of transistors, CPU complexity, therefore higher CPU prices

Question 26

# , Motivation for RISC

Answer 26

As memory capacities grew, there was less need for high code density. Also, pushing clock rates higher on CISC hardware was difficult. A simpler processor could be clocked faster

Question 27

# , – General characteristics of RISC 

Answer 27

1. Lower number of operations (150+) 2. Compilers have more work to do. 3. Small number of instruction formats 4. All instructions take one cycle. 5. Load/store architecture 6. Smaller number of transistors, lower CPU complexity, therefore lower CPU prices

Question 28

# , RISC vs. CISC

Answer 28

https://s3.amazonaws.com/classconnection/655/flashcards/7082655/png/selection_252-14A6227F56E5A3FFFE5.png

Question 29

# , did you know about transistor 

Answer 29

– CISC processors require more CPU transistors in an effort to maximize code density in memory

Question 30

# , did you know about the Risc processor 

Answer 30

RISC processors use a simpler design in an effort to reduce the number of cycles per instruction

Question 31

# , The only major CISC architecture today is

Answer 31

the Intel x86 and x64. Nearly all else is RISC.