Memory Management Flashcards

1
Q

What are the main aspects that distinguish a memory management strategy?

A
  • Sequence of operation
  • Size of pieces
  • Representation of allocation
  • Fragmentation
  • Allocation strategies (with free pieces)
  • (Re)-integration
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2
Q

Describe Sequence of Operation approaches

A

It is the action of allocation and release of memory.

  • In same order: queuing approaches, FIFO
  • In reverse order: Batch approaches, LIFO
  • in arbitrary order: general approach
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3
Q

Describe size of pieces concepts

A
  • Constant size: NUM = 1 (unit size)
  • Multiple of constant size: NUM = k (unit size)
  • Give size of partitions: NUM = k_1, k_2, k_3
  • Arbitrary size: NUM = x
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4
Q

Describe the concept of representation of allocation, give two examples

A
  • How allocation of memory is represented: Using a vector or table
  • Where is allocation of memory represented: Separated or Integrated

In a separated representation by table: information about allocation is stored in a table that is sorted by address and/or length

In an integrated representation by vector: allocation information/pieces identify themselves, specify their lengths and provide pointer to next element of free list. The pointer to next free elements of memory can be sorted by address (next closest free address) or length (next longest free address list)

Example: Main Memory is represented with words of 32 bits

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5
Q

Describe the concept of fragmentation

A

Usually memory is allocated for multiple of units where requests are rounded up to the next multiple of units.

  • Internal fragmentation: The unused parts of the allocated memory.
  • External fragmentation: Overall amount of free memory can satisfy a request but because of the dynamic of allocation and release of pieces, the layout of the free memory can not satisfy a request.
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6
Q

Describe Memory Allocation Strategies and their characteristics

A
  • First Fit Strategy: Search the free list from start and take the first piece of free memory that satisfies the request (low effort, external fragmentation, concentration of allocated memory at beginning of memory space, increased search effort in loaded situations).
  • Next Fit Strategy, Rotating First Fit Strategy: Cyclic search of list that starts from point of last allocation (like First Fit but without concentration at beginning of memory space leading to slightly reduced search effort).
  • Best Fit Strategy: Allocate the smallest piece of memory that satisfies the request. If sorted by address the whole free list will be searched therefore list should be sorted by size of piece of free memory to avoid long search times. Allows for reduced external fragmentation but may produces very small pieces of free memory that can not be used for any future requests.
  • Nearest Fit Strategy: Provided with favored address, search with First Fit from that address.
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7
Q

Describe the concept of Re-integration

A

It is the process of joining up free memory pieces together when one in the middle is released. It can happen instantly after release or delayed.

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8
Q

Describe a ring buffer

A
  • Allocation and release in same direction
  • Fix length of pieces
  • No search needed
  • No external fragmentation
  • Automatic and immediate reintegration
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9
Q

Describe a Stack

A
  • Allocation and release in inverse direction (LIFO)
  • Arbitrary length of pieces
  • No search needed
  • Little external fragmentation
  • Automatic and immediate reintegration
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10
Q

Describe Vector based approach

A
  • Allocation and release in arbitrary direction
  • Fixed length with k * unit size
  • Search for first fitting piece
  • Internal and external fragmentation
  • Automatic and immediate reintegration
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11
Q

Describe boundary tag system and its optimizations techniques.

A

The boundary tag includes labels for:
* free pieces: free label, length of free piece, pointer to next/previous free piece.
* used pieces: used label, length of used piece.
The labels are at the beginning / end of the free and used pieces

  • Operation in arbitrary order
  • Allocation of pieces with arbitrary size (length)
  • Integration of management and representation of pieces (doubly linked list sorted by size of pieces).
  • Best Fit search strategy
  • External fragmentation
  • Explicit immediate reintegration using length labels to check with neighboring pieces (immediate integration into linked list).

Optimizations:
- Transform external fragmentation to internal fragmentation by merging requested piece and small piece.
- Avoid integration of small pieces into the free list but merge them with released
- Reduce cost of search on arbitrary order of allocation and release from O(n) by changing the free list into a binary tree

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12
Q

Describe Buddy System

A
  • Allocation and release in arbitrary order:
  • allocation: Check for next value with power of two, take first entry of list. In case of empty list, take first entry of next list with bigger pieces, cut piece in half and insert second half into list of original size and take remaining for request.
  • release: determine buddy of piece to be released. if buddy is used, insert piece into buddy’s free list. In case buddy is free, join both piece and buddy) and insert emerged piece into next free list.
  • Allocation of pieces with unit size of 2^0, 2^1, 2^2, …, 2^k.
  • Separated representation: Array of heads of free lists for pieces with same size
  • Limited search costs
  • Internal and external fragmentation: Amount of internal fragmentation can be fairly large.
  • Explicit reintegration: Pieces split in one action by joined by release
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13
Q

What is an address space and what is the difference between logical and physical address spaces?

A

An address space is a contiguous set of addresses.

A logical address space is the program address space (from the view of a thread/program) while the physical address space is defined by the width of the address bus.

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14
Q

What is problem when not using logical memory?

How does paging solve it (structure, + and -)
How does segmentation solve it (structure, + and -)

A

Memory management is the responsibility of dividing the memory among the various processes.

The fundamental goal of memory management is to make optimal use of memory by minimizing internal and external fragmentation. At a moment, a single process is loaded into memory. Partition main memory into a set of non-overlapping memory regions called partitions.

Memory can be allocated in contiguous or non-contiguous memory/partitions. Paging and Segmentation are parts of the non-contiguous allocation of memory i.e. it is a memory management technique

Paging:

Paging is a memory allocation method that allows a process’s physical address space to be non-contiguous.
Physical memory is divided into fixed-sized blocks called frames, and logical memory space is divided into fixed-sized blocks called pages.
Paging separates logical and physical addresses, with logical addresses consisting of a page number and offset, and physical addresses consisting of a frame number and offset.
The page table base register (PTBR) refers to a process’s page table, and the page table length register (PTLR) indicates the size of the page table.
Every new process creates a separate page table, which is stored in physical memory and contains the base address of each page.
Characteristics of paging include no external fragmentation, non-contiguous memory allocation, and potential internal fragmentation on the last page of a process.
Advantages of paging include effective memory management, simplicity in partitioning, and simple and inexpensive memory allocation.
Disadvantages of paging include internal fragmentation, address translation using specialized hardware, and longer memory access times.

Segmentation:

Segmentation divides the virtual address space of a process into variable-sized segments that correspond to logical units of the program.
Segments must be loaded into memory before a program can run.
Address mapping is done with a segment table, indicated by the segment-table base register (STBR) and the segment-table length register (STLR).
Advantages of segmentation include no internal fragmentation, efficient translation, and the ability to protect and share different segments.
Disadvantages of segmentation include external fragmentation and expensive memory management.
The program's main function, utility functions, data structures, and so on are all contained within a program segment.
The segment table is smaller than the table used in paging, and the OS keeps a segment map table and a list of free memory blocks for each process.
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15
Q

What is the difference between regular page table and inverted page table?

A

In virtual memory management, a page table is a data structure used by the operating system to store the mapping between logical and physical addresses of a process. A regular page table stores the mapping information for each page of the process in a separate table entry, which means that for a process with a large number of pages, the page table can become very large.

On the other hand, an inverted page table is a page table implementation that maintains a single table for all the processes in the system. Rather than having a separate table entry for each page of a process, an inverted page table has an entry for each physical frame in memory, which stores the process ID and page number that maps to that frame. This means that the size of the page table is proportional to the number of physical frames in memory rather than the number of pages in the process.

The main advantage of the inverted page table is that it can reduce the memory overhead associated with maintaining a separate page table for each process. However, it is more complex to implement and requires additional processing time for page table lookups, as it requires a search through the entire table to find the mapping for a given process and page number.

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16
Q

What is the problem with address translation and how to make it more efficient?

A

Translation Lookaside Buffer (TLB) is a hardware cache that stores the recently used page table entries (PTEs) to improve the performance of virtual memory translation. The TLB is typically located in the memory management unit (MMU) and used in conjunction with the page table to translate virtual memory addresses to physical memory addresses.

When a process accesses memory, the processor generates a virtual address that needs to be translated to a physical address by checking the page table. The page table lookup process can be slow, especially if the page table is large and resides in main memory. The TLB cache solves this problem by storing the most recently used page table entries in a small, fast cache.

When a virtual address is generated, the processor first checks the TLB cache to see if the corresponding physical address is present in the cache. If the entry is found, the translation is done quickly, without accessing the page table in main memory. If the entry is not found, the processor will access the page table to retrieve the corresponding physical address and store it in the TLB cache for future use.

The TLB significantly speeds up virtual memory translation by reducing the number of memory accesses needed to access the page table. Without a TLB, every memory access would require a full page table lookup, which could be prohibitively slow. The TLB is an essential component of modern computer architecture, allowing for efficient use of virtual memory and improving overall system performance.

17
Q

Explain memory hierarchy, mention the hierarchies (with who is responsible for data transport and unit of transport), what happens on access and modification, the principle of locality.

A

From slower, larger, cheaper to faster, small and more expensive:

Archive (DVD, tape)
<-(OS, user via files)>
Magnetic or Solid State Disk
<-(OS via Blocks)>
Main Memory
<-(HW via Cache-Lines)>
Caches (multiple levels)
<-(HW via Words)>
Processor Register

On (first) access: data objects is copied from lower to higher levels.
On modification: changes are propagated from higher to lower levels.

this hierarchy is based on the principle of locality where a program limits its accesses within a small time interval (temporal locality, access to an address a then repeated access to same address within short time is very likely) to only a small subset of its address space (spatial locality, access to address a then access to nearby address is very likely)

18
Q

Explain the concept of virtual memory

A

The user / programmer has the impression that main memory is available in unlimited size. This is only virtually existent as pages of programs (pages are the units of transfer) are loaded into main memory only when addressed due to the principle of locality that says only those parts of the address space that are currently used by a program need to be present in the physical memory.

19
Q

Explain difference between caching and virtualization

A

Caching is performed to accelerate the data access while virtualization is used to enlarge the capacity to access data.

20
Q

Explain the difference between volatile and permanent memory and how caching and virtualization affect those two concepts.

A

memory in higher levels of the hierarchy is usually volatile (temporary data) while memory in lower level is permanent (permanent data). Volatile memory means data is lost within the memory when power is cutoff.

Using caching and virtualization led to weaken the difference between main memory (for address spaces only and not actual data) and disc space (for files only)

21
Q

What are the requirements for efficient virtual memory

A
  • Noncontinguous allocation in physical memory using page tables
  • Automatic detection of missing pages: Access to missing pages triggers an interrupt where loading of the missing page is initiated as part of the interrupt handling
22
Q

What are the components and data structures that allow for virtual memory and what is in their content

A
  • Page table: address transformation from logical to physical. includes for each page its physical address, a bit that indicates whether a page is present in main memory or not, a reference bit that indicates whether page has been accessed or not and modification/dirty bit that indicates whether the page has been modified or not.
  • Page frame table: memory management. includes for each page frame its state (free / occupied), owner and occupying page.
  • Swap/Paging area: A swap or paging area is a portion of a hard disk or solid-state drive that is reserved for use as a backup memory space for the operating system. It is used when there is not enough physical RAM to hold all the running programs and data, and the system needs to swap out some of the memory pages to the swap area in order to free up space.

When a program requests a page that is not currently in the physical RAM, the operating system will retrieve it from the swap area and bring it into the RAM. This process is called paging or swapping. Similarly, when a program is inactive and its pages are not being used, the operating system may decide to swap out those pages to the swap area to free up space in the RAM.

23
Q

What is a segmentation fault?

A

A segmentation fault is an interrupt that occurs when a program attempts to access a memory location that it is not allowed to access. For example, in the segment table, there’s a length field that indicates the appropriate amount of memory for each logical address, exceeding this length triggers a segmentation fault.

24
Q

What is a page fault? How can buffering help? What does page fault rate depend on?

A

When a process tries to reference a page not currently present in RAM, the processor treats this invalid memory reference as a page fault (interrupt). The interrupt handling is as following:

  • Determine the location of the data on disk.
  • Obtain a free page frame (if not available then select a page frame to be cleared, when found and its content was modified then move it to page area to be written on disk)
  • Load the new page from disk
  • Update the page frame table and page table to refer to the new page.

The steps can be divided into getting a page out to the page area to be swapped out then swapping in the requested page from disk.

Since page faults often occur in bulks, we apply the buffering principle to get a stock of free page frame to avoid costly page-out operations when time is tight.

The page fault rate strongly depends on which pages are kept in real memory and which are stored on disk.

25
Q

What are the types of page selection/replacement strategies? Provide some examples!

A

Two types:
- Local selection strategy: Clear a page frame of the process that causes the page fault.
- Global selection strategy: Clear an arbitrary page frame (may belong to other processes).

Classical Strategies:
- FIFO: Page longest in memory is swapped out
- LFU: Least Frequently used (referenced) page is swapped out
- LRU: Least Recently used (referenced) page is swapped out
- RNU: Recently not used (referenced) page by some specified time is swapped out

Smarter Strategies:
- Second-Chance-Algorithm (Clock-Algorithm): Cyclically scan the reference bits of pages with a pointer in page table to reset reference bits to 0. Pages have until the next linear cycle search to get referenced again (second chance which gets their reference set to 1) to stay in memory. The page to be swapped out in the next page in the linear pointer search to have a reference bit of 0.

26
Q

When does virtual memory work the better in terms of efficiency?

A

The virtual memory works the better, the higher the programs locality. And locality is good if few pages are referenced with high probability and many pages with low probability. Meaning that page swapping and time needed for it remains minimal. This would increase the hit probability and lower the page fault probability.

27
Q

What Thrashing? When does it happen.

A

Thrashing is an overload phenomenon that happens when the system (processor) is completely occupied with paging (swapping) and can not perform regular useful work. This leads to poor processor utilization.

When many programs are executed simultaneously (high degree of multiprogramming), every process has low memory space associated to it, meaning that there is short time intervals between successive page faults leading to congestion at paging device (disk) due to frequent page swapping rendering almost all process blocked and that’s how we get poor processor utilization.

28
Q

How to prevent thrashing? What are the two types of strategies?

A

The multiprogramming level must be limited.
So limit simultaneously running threads/processes by n_max. But how to find optimal n_max?

n_max is adopted dynamically during runtime. So thrashing prevention is done by feedback control. There are two main strategies:

  • Indirect/Local Strategy: For each process, determine a reasonable number of frames dynamically and use it to find the maximum multiprogramming level
  • Direct or global strategy: Measurement of the global paging activity leads to the calculation of an optimal n_max.
29
Q

Discuss indirect/local thrashing prevention strategies?

A
  • Working-Set model:
    Working-Set of a program/process is defined as the set of pages that been referenced with the last x time units. With suitable choice of x, we can find the number of page frames needed for the program to run efficiently. Then a new process is loaded into memory only if its working-set does not exceed the max value of working set minus the current working sets of running processes.
  • Page- Fault Frequency Model: For each process, page fault rate is measured and serves to adjust the number of frames (increase working set if page fault rate is above a certain value and decrease it if rate is below certain value). This allows to calculate the multiprogramming level.
30
Q

Discuss global/direct thrashing prevention strategies?

A
  • 50% Rule: New processes are loaded into main memory only if the utlization of the disk is below 50% (when utilization is higher than 50% it means there’s a lot of paging activity to swap pages between disk and main memory which leads to thrashing).
  • Parabola approximation: Using an estimated parabola by taking measurements in the region of the maximum of processor utilization curve (Y axis, max 1) by # of concurrent programs (X axis, max n). The apex n* of the estimated parabola is calculated and used as upper bound of the multiprogramming level.