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Computer Science year 1 > SCC131: weeks 1-6 > Flashcards

SCC131: weeks 1-6 Flashcards

computer architecture (91 cards)

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1
Q

what is an architecture in computing?

A

the science of putting together hardware components for optimal computer performance.
-dependant on the requirements of the machine.

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2
Q

what is ENIAC?

A

Electronic numerical integrator and computer- developed during WW2

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3
Q

What were the limits of ENIAC?

A

-no storage capability, only processing
-programmed via switches and cables (advancement on punch cards)

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4
Q

describe the computer architecture

A

set of rules and methods that describe the functionality, organisation and implementation of computer systems

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5
Q

where can computer architecture be applied?

A

-component level: processor, memory, instruction set
-system level: linking processor to internal/external devices

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6
Q

what is von neumann architecture?

A

JOINT MEMORY FOR STORING DATA AND INSTRUCTIONS

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7
Q

what is harvard architecture?

A

SEPARATE MEMORY FOR DATA AND INSTRUCTIONS

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8
Q

what are the benefits of using a harvard architecture?

A
  • if memory is targeted during an attack, it is more difficult for both portions of memory to be accessed
    -parallel access to instruction and data memory can speed up processing and avoid bottleneck issue of von neumann
  • more expensive though
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9
Q

what is the benefit of von neumann architecture?

A

easier to program to

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10
Q

how can processor speed be measured?

A

-clock rate: 1.87 GHz does 1.87 billion ticks a second
-MIPS (millions of instructions per second): more reliable measure than clock rate
-FLOPS(floating point operations per second)
None take input/output speed into account

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11
Q

list some of the limiting factors on speed

A

-density limitations
-power limitations
-numbers of processors
-coarser grained parallelism, clustering

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12
Q

describe how density limitations impact the performance of a computer

A

transistors are semiconductors, the more you have, the faster the computer

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13
Q

describe how power limitations impact the performance of a computer?

A

-1/3 of all power is used to propagate the clock signal around the processor
-heat problems increase proportionally to the clock speed, cooling methods are needed
- more semiconductors = more heat

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14
Q

how does the number of processor cores impact the performance of the computer

A

allows for parallel processing, which increases functioning of computer

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15
Q

describe coarser grained parallelism

A
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16
Q

why is binary used in computer systems?

A

-binary can be generated using high and low voltage
-method of representing a wide range of media

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17
Q

what does ASCII stand for

A

american standard code for information interchange

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18
Q

what is IEEE 754

A

-institute of electrical and electronics engineers
-international standard for generating floating point numbers

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19
Q

how is IEEE 754 generated?

A

-32 bits used
-8 bit exponent + 1 bit to indicate sign
-23 bit mantissa, using excess n

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20
Q

what is used to construct computer logic?

A
  • Transistors
  • vacuum tubes
  • electro mechanical relays
    -sheet metal
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21
Q

how do you perform perfect induction?

A

by testing every possible combination of a boolean expression

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22
Q

what are the steps for designing a logic circuit?

A

-write out a truth table
-derive boolean expression by ORing the rows with a True output (or draw a k map)
-simplify expression
-translate into logic gates

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23
Q

how can nand gates be translated into transistors?

A
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24
Q

what are the two main expressions related to de morgans law?

A
  • (AB)’ = A’+B’
  • (A+B)’ = A’ B’
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25
what are the three steps of implementing de morgans law?
1. negate whole expression 2.negate sub expressions 3. flip operators from or to and or other way
26
what is a computer's instruction set architecture?
-set of instructions -available registers -how many operands are required for instructions -size and type of operations -how many clock ticks are needed for a single instructions
27
what is RISC
reduced instruction set computers
28
what do RISC ISAs consist of?
-small number of instructions with common operand format -all instructions except LOAD and STORE operate on registers - 1 clock cycle to execute instruction
29
why are registers needed?
-storage spaces for data needed for instructions being carried out in the CPU. -Faster than accessing data in main memory -ALU instructions often designed to work only on values within registers.
30
What are the general purpose registers used for?
storing values/results for arithmetic and logical operations
31
list the special purpose registers
-PC -CIR -MDR -MAR
32
what is MIPS?
Microprocessor without interlocked pipeline stages
33
what constitutes a MIPS?
- type of ISA -32 registers, 32 bits in each -categorised as a RISC -no floating point capability
34
what are the three types of instructions used in a MIPS instruction set
-Arithmetic and logic -Data transfer -Control transfer
35
what are data transfer instructions of a MIPS instruction set used for?
transferring data between registers and main memory
36
what are control transfer instructions in a MIPS architecture used for?
by default instructions are executed sequentially- control transfer instructions allow changes to be made to the default execution path
37
what is the function of PC?
storing memory address of the next instruction to be executed by the processor
38
how is the value of the PC used during subroutine calls?
before making a call to a subroutine (likely using a different location in memory) value of the PC is noted as a return value for after subroutine completion
39
how are nested subroutine calls handled?
call stack is used to make note of return addresses from the PC
40
What is the difference between a half adder and a full adder?
a half adder can only be used to add 2 bits, when a bit is carried and a third needs to be added, a full adder must be used.
41
what is the role of the status register?
holds negative, overflow and zero error flags.
42
what is it shifting?
enables fast multiplication division by powers of two
43
list the types of bit shifts
-arithmetic shift -logical shift -rotate -rotate through carry
44
what are the two types of volatile memory?
-dynamic memory -static memory
45
give an example and a pro/con of dynamic memory.
-main memory, RAM -slower than static memory, but cheap.
46
give an example and a pro/con of static memory.
-registers and cache -faster than dynamic memory, but expensive
47
describe the concept of combinatorial logic
it's outputs are a function of it's inputs
48
describe the concept of sequential logic
outputs are a function of it's inputs AND it's current outputs -feedback of outputs as an INPUT to the function -feedback is a *hook* on which we hang memory
49
-describe an S-R flip flop circuit
-inputs S (set) and R (reset) -both inputs are split and fed to an individual nand gate -the outputs are fed into two separate and gates, with the second input to both being the feedback from the and gates' output, Q.
50
what happens when S is a high pulse on an S-R flip flop?
-Q = 1 -Set
51
what happens if there is a high pulse on R in an S-R flip flop?
-Q = 0 -Reset
52
What are the two main ways multi-byte 'words' can be organised in memory by differing machine architectures?
-Big-endian -Little-endian
53
What does 'Big-endian' mean in memory storage?
-the memory location (byte) -with the lowest/smallest memory address -holds the Most Significant byte (MSbyte) -of the value being stored
54
What does 'Little-endian' mean in memory storage?
--the memory location (byte) -with the lowest/smallest memory address -holds the Least Significant byte (LSbyte) -of the value being stored
55
what are the components of a d-type flip flop?
-output Q -data D -latch
56
what is the function of the latch in a d-type flip flop?
-indicates when data needs to be stored
57
what happens if the latch is high in a d-type flip flop?
the value of data is stored- the output Q matches the value of D
58
what is an M-S flip flop?
-two consecutive d-type flip flops -the latch value split and nanded then passed to the second d-type flip flop as the latch value. -the output of the second flip flop is anded with an 'output enable' value
59
what is the purpose of an M-S flip flop?
-handles the issue of data being overwritten that first needs to be read- like with ADD A,A,10 -Q is only readable if the output enable is high
60
in an M-S flip flop, what happens when the latch is high, versus when the latch is low?
high- data signal is stored to the left, right is unaffected low- data in the left moves to the right
61
what is the purpose of busses?
-connection between internal components of CPU -each bus is a collection of parallel wires, each one used to send a single bit
62
describe the address bus:
-unidirectional -between the control unit and main memory -carries the address needing to be read from/ written to -width of address bus n determines number of addressable memory locations- 2^n locations
63
describe the data bus:
-bidirectional- carries data to and from memory -n-bit processor has a data bus of n width, the amount of data that can physically be processed at once is the maximum amount data bus can carry -data busses external to the CPU may be narrower
64
what does the control unit do?
controls and sequences other architectural modules using their control lines (control busses)
65
list some operations that would occur within the fetch and decode portion of the FDE cycle:
-getting the address of an instruction -read op-code -op-code stored in instruction register
66
give a few examples of instructions in the execute portion of the FDE cycle:
-pc, current memory address, is incremented -get the address of op code from pc -read operand into MDR from RAM -add value in MDR to a register -increment pc
67
what is FSM (finite state machine) based control unit?
- hard wired sequential logic -high performance but difficult to adapt
68
what is a microcoded control unit?
-sequence of micro instructions in micro memory -lower performance, more flexible- easy to add new instructions
69
what are FSM based and microcoded examples of?
-implementations of the FDE cycle
70
describe the concept of pipelining
-process of running multiple instructions concurrently -as different processes require different hardware at different times
71
give some hazards to pipelining
-control hazards -data hazards -structural hazards
72
what are control hazards to pipelining
when a control transfer instruction alters the flow of execution.
73
what are data hazards in pipelining
-when instruction n depends on the result of n-1 -two parts of the pipeline need access to the same data
74
what are structural hazards in pipelining?
two parts of the pipeline require access to the same hardware
75
what happens when a pipeline hazard occurs?
-pipeline stalls -needs to be flushed (reset)
76
give some examples of input devices
-keyboard -mice -touch screen -microphones -cameras
77
give a few examples of output devices
-monitor -speaker -printers -environmental actuators
78
give an example of input/output devices
-network interfaces -MIDI devices
79
what are some challenges for I/O devices?
-speed-gap challenge -device diversity challenge
80
describe the speed-gap challenge in relation to I/O devices:
-I/O devices usually run orders of magnitude slower than the CPU -CPU must be slowed down when dealing with I/O devices
81
describe the device diversity challenge in relation to I/O devices
-how do we deal with differences in function between I/O devices? -diversity in data-access -device specific operations -I/O protocol diversity - (synchronous/asynchronous)
82
what are some potential different types of data access for I/O devices?
-read only/write only/read + write ? -data access by bytes or by blocks/stream ?? -random or sequential access ??
83
what are two typical classifications of devices?
-Character devices: send/receive 1 byte at once -block devices: send/receive multi-byte blocks at once
84
what are device drivers?
-software plug-ins for an OS -many functions incl. ---registering devices with the OS ---initiating data transfers to/from devices
85
how do device drivers deal with device diversity for I/O devices?
-abstracts over device diversity by grouping devices that are somewhat similar ------character/block devices
86
what are two typical classifications for processor support for I/O devices?
-Isolated I/O -memory mapped I/O
87
what is Isolated I/O?
-processor I/O support provided by the processor -physical pins for connecting I/O devices -dedicated instructions for I/O operations
88
what is a drawback of using isolated I/O?
-there exists only a fixed set of I/O specific instructions, which is bad for device diversity
89
What is memory mapped I/O?
-processor support for I/O -I/O devices sit within CPU's linear memory address space -simple and flexible, good for device diversity
90
what is a drawback of memory mapped I/O as a method of processor I/O support?
-adds complexity to devices
91

Computer Science year 1 (17 decks)

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