SCC131: weeks 13-18 Flashcards

(45 cards)

1
Q

What does CISC stand for and what is it?

A

-complex instruction set computing
-a complex instruction set architecture

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2
Q

what are key features of a CISC architecture?

A

-complex instruction set
-one instruction executes multiple low-end operations
-parallel processing pipelines
-higher processor speed at lower clock rate

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3
Q

what does RISC stand for and what is it?

A

-reduced instruction set computing
-reduced complexity instruction set, small and optimised

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4
Q

what are key features of a RISC architecture?

A

-reduced instruction set
-simple pipeline, higher software complexity
-power/heat efficient

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5
Q

is ARM RISC or CISC?

A

-ARM is von neumann and RISC

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6
Q

Why are registers used in ARM assembly?

A

-ALU cannot directly process data from RAM, it needs to be loaded into the registers first.

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7
Q

How many registers does ARM utilise?

A

-16
-R0-R12
-SP (R3)
-LR (R4)
-PC (R5)

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8
Q

what is R13- SP?

A

-stack pointer
-keeps track of the lowest address occupied on the stack/ top value

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9
Q

what is R14- link register?

A

-holds the return address after a subroutine is completed

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10
Q

what is R15- program counter?

A

-holds the memory address of the instruction to be executed next

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11
Q

what does CPSR stand for and what does it do?

A

-current program status register
-ARM register that records the state of a program
-indicates when errors occur

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12
Q

What are the flags that the CPSR can show?

A

-N-bit: result was negative
-Z-bit: result was 0
-C-bit: instruction resulted in a bit being carried
-V-bit: result of calculation caused overflow

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13
Q

how can the program flow be influenced in Assembly?

A

-using branching
-manipulating the PC, changing which instruction will be executed next

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14
Q

how is conditional branching done with Assembly?

A

-using the compare, cmp opcode
-then a conditional branch

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15
Q

check memory arm

A
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16
Q

define a function

A

-a stored subroutine that performs a specific task based on parameters
-modularity

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17
Q

what are some function calling conventions in assembly?

A

-r0-r3 reserved for arguments and parameters
-r0 is reserved for a return value
-lr return address register, stores the address of the instruction to be returned to after execution of the function is finished

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18
Q

what are memory usage conventions for assembly?

A

preserved memory:
—r4–>r11
—SP, r13
—return address, LR or r14
—stack above SP
non-preserved memory:
—temp register, r12
—args register r0-r3
—status register
—stack below SP

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19
Q

what is register spilling?

A

-when more than 4 registers are needed, main memory can be used
-this involves using the stack

20
Q

when MUSTregister spilling be used?

A

-when nested functions are used, to preserve the original return address, the contents of the lr must be pushed to the stack
-if this is not done, the original return address will be lost.

21
Q

what are the arm opcodes for putting things onto/taking things off the stack?

A

-push {r4,r5,lr}
-pop {r4,r5,lr}

22
Q

inline assembly

23
Q

what is moore’s law?

A

the number of transistors on an integrated circuit doubles about every two years

24
Q

what are the three types of MIPS machine code instructions?

A

-register type (R-type)
-Immediate type (I-type)
-Jump type (J-type)

25
what controls program flow?
-PC
26
what are exceptions?
-hardware or software components that require CPU attention -can be thought of as unscheduled function calls that branch to a new address -an unexpected change in program flow control
27
what are the two main types of exceptions?
-synchronous (essentially software interrupts) -asynchronous (essentially hardware interrupts)
28
what is the need for privilege levels in the CPU?
-protecting the computer's resources from unauthorised access -full resource access is not granted to all code
29
what can be used to request a higher level of access from the operating system?
-supervisor call instruction (SVC)
30
how are interrupts handled?
-FDE cycle paused -CPU state is preserved -Code is run to manage interrupt
31
how does computer know how to deal with specific interrupt?
-vector table in low memory used as a lookup table to find memory address to execute when specified interrupt occurs
32
in arm, how is the execution mode shown?
-specified in CPSR
33
how are exception handlers similar to other normal functions?
-still needs a return address -still needs to preserve registers
34
what is the problem with using the stack for exception handlers?
-stack is located in memory and is relatively slow
35
what is an FIQ?
-fast interrupt request -low latency interrupt handling for ARM -uses banked registers to copy values from registers when an interrupt occurs
36
what are some of the program states stored in CPSR?
- IRQ flag: I-bit, disables IRQ interrupts - FIQ flag: F-bit , disables FIQ interrupts -Thumb flag T-bit, disables
37
what is MMIO?
-mechanism that facilitates input/output between CPU and peripherals -hardware devices are mapped to specific memory addresses
38
what do interfaces do with reference to MMIO?
-device is ready to receive new data from host -host is ready to receive new data from device
39
what do protocols do with reference to MMIO?
-determine the meaning of signals from peripherals -can be command or data signal
40
what is handshaking for protocols?
-protocol being agreed upon -receiver acknowledges that data has been sent/ indicates it is ready to receive data
41
what is the name for the memory assigned to a device in MMIO?
-I/O register -data transfers involves storing data at the device's I/O register
42
what is Polled I/O?
-status register related to a port is monitored by CPU -CPU "polls" status registers (checks them at regular intervals)
43
what is Interrupt I/O?
-device uses interrupts (asynchronous signals) to indicate to CPU when data is ready to send -CPU does not need to check on devices
44
what are the two types of I/O communication for peripherals?
-Interrupt I/O -Poll I/O
45
LED operation