Structure and function of the processor Flashcards

1
Q

define hardware

A

the physical components which make up a computer system

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2
Q

define register

A

an area of very fast memory inside the CPU itself which temporarily stores small amounts of binary data

all arithmetic, logical, or shift operations take place in registers

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2
Q

define CPU

A

central processing unit
has a number of different components which enable it to carry out its task of executing instructions

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3
Q

define motherboard

A

the main system board which connects all the hardware components

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3
Q

define register exam answer

A
  • temporary storage/memory location
  • inside the CPU
  • used for a single specific purpose
  • faster access speed than RAM/secondary storage
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4
Q

what is the purpose of the control unit (CU)?

A

direct the operations of the CPU:
- controlling and coordinating the activities of the CPU
- managing the flow of data between the CPU and other devices
- accepting the next instruction
- decoding instructions
- storing the resulting data back in memory

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5
Q

what is the purpose of the arithmetic logic unit (ALU)?

A

completes all of the arithmetical and logical operations.

A: all mathematical operations such as addition and subtraction on fixed or floating point numbers

L: boolean logic operations such as AND, OR, NOT, and XOR

also, shift operations on bits

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5
Q

what is the purpose of the program counter (PC)?

A

holds the address of the next instruction to be executed

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6
Q

what is the purpose of the accumulator (ACC)?

A

temporary storage for data being processed during calculations/stores the result

  • for I/O in processor, it acts as a buffer (holds data that is on its way to somewhere else)/gateway
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7
Q

what is the purpose of the memory address register (MAR)?

A

holds the address of a location that is to be read from or written to

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8
Q

what is the purpose of the memory data register (MDR)?

A

temporarily stores data that has been read or data that needs to be written

  • acts as a buffer (memory designed to hold data that is on its way to somewhere else)
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9
Q

what is the purpose of the current instruction register (CIR)?

A

holds the current instruction being executed, divided up into operand and opcode

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9
Q

what is the width of a bus?

A

the number of parallel wires the bus has.

the width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time

buses are typically 8, 16, 32 or 64 wires wide

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10
Q

define bus

A

a set of parallel wires which connect two or more components inside the CPU
- data bus
- address bus
- control bus
^collectively called system bus

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11
Q

what is the data bus?

A

a bi-directional bus used for transporting data and instructions between components

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11
Q

what is the control bus?

A

a bi-directional bus used to transmit control signals between internal and external components.

its purpose is to transmit command, timing and specific status information between system components

11
Q

what is the address bus?

A

the bus used to transmit the memory addresses specifying where data is to be sent to or retrieved from.

the width of the address bus is proportional to the number of addressable memory locations

12
Q

what are the control lines?

A

bus request: indicates that a device is requesting the use of the data bus
bus grant: indicates that the CPU has granted access to the data bus
memory write: causes data on the data bus to be written into the addressed location
memory read: causes data from the addressed location to be placed on the data bus
interrupt request: indicates that a device is requesting access to the CPU
clock: used to synchronize operations

12
Q

what is assembly language?

A

uses mnemonics to represent instructions - a simplified way of representing machine code.

the instruction is divided into operand and opcode in the CIR

13
Q

what is the opcode?

A

specifies the type of instruction to be executed

14
Q

what is the operand?

A

contains the data or the address of the data upon which the operation is to be performed.

15
Q

what is the fetch-decode-execute cycle?

A

the sequence of operations that are completed to execute an instruction

16
Q

what is involved in the fetch phase?

A
  • The address of the next instruction is copied from the PC to the MAR
  • instruction held at that address is copied to MDR by the data bus
  • simultaneously, the contents of the PC is incremented
  • the value held in the MDR is copied to the CIR
17
Q

what is involved in the decode phase?

A

the contents of the CIR are split into operand and opcode

opcode is used to determine the type of instruction and what hardware to use to execute it

operand holds either:
- actual data to be operated on
- address of data to be used within the operation

18
Q

what is involved in the execution phase?

A

the appropriate instruction/opcode is carried out on the operand

19
Q

what is pipelining?

A

the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously, holding appropriate data in a buffer near the CPU until it’s required. while one instruction is being fetched, the previous could be decoded and the one before that, executed.

aims to reduce the amount of the CPU which is kept idle.

20
Q

what can pipelining be separated into?

A

instruction pipelining and arithmetic pipelining

instruction pipelining is separating out the instruction into fetching, decoding, and executing

arithmetic pipelining is breaking down the arithmetic operations and overlapping them as they are performed

21
Q

what is the pipelining exam answer?

A
  • concurrent processing of multiple instructions
  • one instruction can be fetched while the previous is being decoded…
  • …and the one before is being executed
  • in the case of a branch, the pipeline is flushed
  • increases the speed of execution
22
Q

what problems can arise from pipelining?

A

when branch or jump instructions occur:
- could be followed by one of two possible instructions; which will only be determined at execution
- this means the wrong one may be fetched/decoded while using pipelining