analog to digital - computer Flashcards
(123 cards)
1
Q
The two basic types of signals are analog and:
digilog
digital
vetilog
sine wave
A
digital
2
Q
Which of the following characterizes an analog quantity?
Discrete levels represent changes in a quantity.
Its values follow a logarithmic response curve.
It can be described with a finite number of steps.
It has a continuous set of values over a given range.
A
It has a continuous set of values over a given range.
3
Q
ASCII stands for:
American Serial Communication Interface
Additive Signal Coupling Interface
American Standard Code for Information Interchange
none of the above
A
American Standard Code for Information Interchange
4
Q
Which type of signal is represented by discrete values?
noisy signal
nonlinear
analog
digital
A
digital
5
Q
A data conversion system may be used to interface a digital computer system to:
an analog output device
a digital output device
an analog input device
a digital printer
A
an analog output device
6
Q
Sample-and-hold circuits in ADCs are designed to:
sample and hold the output of the binary counter during the conversion process
stabilize the ADCs threshold voltage during the conversion process
stabilize the input analog signal during the conversion process
sample and hold the ADC staircase waveform during the conversion process
A
stabilize the input analog signal during the conversion process
7
Q
The weight of the LSB as a binary number is:
1
2
3
4
A
1
8
Q
What is the difference between binary coding and binary coded decimal?
Binary coding is pure binary.
BCD is pure binary.
Binary coding has a decimal format.
BCD has no decimal format.
A
Binary coding is pure binary.
9
Q
A single transistor can be used to build which of the following digital logic gates?
AND gates
OR gates
NOT gates
NAND gates
A
NOT gates
10
Q
How many NAND circuits are contained in a 7400 NAND IC?
1
2
4
8
A
4
11
Q
Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
OR gates only
AND gates and NOT gates
AND gates, OR gates, and NOT gates
OR gates and NOT gates
A
AND gates, OR gates, and NOT gates
12
Q
Which statement below best describes a Karnaugh map?
It is simply a rearranged truth table.
The Karnaugh map eliminates the need for using NAND and NOR gates.
Variable complements can be eliminated by using Karnaugh maps.
A Karnaugh map can be used to replace Boolean rules.
A
It is simply a rearranged truth table.
13
Q
The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as:
A
DeMorgan’s second theorem
14
Q
The systematic reduction of logic circuits is accomplished by:
symbolic reduction
TTL logic
using Boolean algebra
using a truth table
A
using Boolean algebra
15
Q
How many inputs are required for a 1-of-10 BCD decoder?
4
8
10
1
A
4
16
Q
Most demultiplexers facilitate which of the following?
decimal to hexadecimal
single input, multiple outputs
ac to dc
odd parity to even parity
A
single input, multiple outputs
17
Q
One application of a digital multiplexer is to facilitate:
code conversion
parity checking
parallel-to-serial data conversion
data generation
A
parallel-to-serial data conversion
18
Q
Select one of the following statements that best describes the parity method of error detection:
Parity checking is best suited for detecting single-bit errors in transmitted codes.
Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
Parity checking is not suitable for detecting single-bit errors in transmitted codes.
Parity checking is capable of detecting and correcting errors in transmitted codes.
A
Parity checking is best suited for detecting single-bit errors in transmitted codes.
19
Q
A multiplexed display:
accepts data inputs from one line and passes this data to multiple output lines
uses one display to present two or more pieces of information
accepts data inputs from multiple lines and passes this data to multiple output lines
accepts data inputs from several lines and multiplexes this input data to four BCD lines
A
uses one display to present two or more pieces of information
20
Q
When two or more inputs are active simultaneously, the process is called:
first-in, first-out processing
priority encoding
ripple blanking
priority decoding
A
priority encoding
21
Q
Which type of decoder will select one of sixteen outputs, depending on the 4-bit binary input value?
A
hexadeciml
22
Q
A circuit that responds to a specific set of signals to produce a related digital signal output is called a(n):
BCD matrix
display driver
encoder
decoder
A
encoder
23
Q
Which digital system translates coded characters into a more intelligible form?
encoder
display
counter
decoder
A
decoder
24
Q
A basic multiplexer principle can be demonstrated through the use of a:
single-pole relay
DPDT switch
rotary switch
linear stepper
A
rotary switch
25
In a BCD-to-seven-segment converter, why must a code converter be utilized?
No conversion is necessary.
to convert the 4-bit BCD into gray code
to convert the 4-bit BCD into 10-bit code
to convert the 4-bit BCD into 7-bit code
to convert the 4-bit BCD into 7-bit code
26
Which of the following is correct for a gated D-type flip-flop?
The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
The output complement follows the input when enabled.
Only one of the inputs can be HIGH at a time.
The output toggles if one of the inputs is held HIGH.
The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
27
When both inputs of a J-K flip-flop cycle, the output will:
be invalid
not change
change
toggle
not change
28
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
asynchronous operation
low input voltages
gate impedance
cross coupling
cross coupling
29
The 555 timer can be used in which of the following configurations?
astable, monostable
monostable, bistable
astable, toggled
bistable, tristable
astable, monostable
30
A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
AND or OR gates
XOR or XNOR gates
NOR or NAND gates
AND or NOR gates
NOR or NAND gates
31
One example of the use of an S-R flip-flop is as a(n):
transition pulse generator
astable oscillator
racer
switch debouncer
switch debouncer
32
If both inputs of an S-R NAND latch are LOW, what will happen to the output?
The output would become unpredictable.
The output will toggle.
The output will reset.
No change will occur in the output.
The output would become unpredictable.
33
An astable multivibrator is a circuit that:
has two stable states
is free-running
produces a continuous output signal
is free-running and produces a continuous output signal
produces a continuous output signal
34
.
What is another name for a one-shot?
monostable
bistable
astable
tristable
monostable
35
The truth table for an S-R flip-flop has how many VALID entries?
3
1
4
2
3
36
What is the significance of the J and K terminals on the J-K flip-flop?
There is no known significance in their designations.
The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH.
The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
All of the other letters of the alphabet are already in use.
There is no known significance in their designations.
37
Which of the following describes the operation of a positive edge-triggered D-type flip-flop?
If both inputs are HIGH, the output will toggle.
The output will follow the input on the leading edge of the clock.
When both inputs are LOW, an invalid state exists.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
The output will follow the input on the leading edge of the clock.
38
What is one disadvantage of an S-R flip-flop?
It has no Enable input.
It has a RACE condition.
It has no clock input.
It has only a single output.
It has a RACE condition.
39
A ripple counter's speed is limited by the propagation delay of:
each flip-flop
all flip-flops and gates
the flip-flops only with gates
only circuit gates
each flip-flop
40
To operate correctly, starting a ring counter requires:
clearing all the flip-flops
presetting one flip-flop and clearing all the others
clearing one flip-flop and presetting all the others
presetting all the flip-flops
presetting one flip-flop and clearing all the others
41
What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
PIPO
SISO
SIPO
PISO
SISO
42
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
input clock pulses are applied only to the first and last stages
input clock pulses are applied only to the last stage
input clock pulses are not used to activate any of the counter stages
input clock pulses are applied simultaneously to each stage
input clock pulses are applied simultaneously to each stage
43
One of the major drawbacks to the use of asynchronous counters is that:
low-frequency applications are limited because of internal propagation delays
high-frequency applications are limited because of internal propagation delays
Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.
Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.
high-frequency applications are limited because of internal propagation delays
44
Which type of device may be used to interface a parallel data format with external equipment's serial format?
key matrix
UART
memory chip
serial-in, parallel-out
UART
45
When the output of a tri-state shift register is disabled, the output level is placed in a:
float state
LOW state
high impedance state
float state and a high impedance state
float state and a high impedance state
46
A comparison between ring and johnson counters indicates that:
a ring counter has fewer flip-flops but requires more decoding circuitry
a ring counter has an inverted feedback path
a johnson counter has more flip-flops but less decoding circuitry
a johnson counter has an inverted feedback path
a johnson counter has an inverted feedback path
47
A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
shift register sequencer
clock
johnson
binary
shift register sequencer
48
What is meant by parallel-loading the register?
Shifting the data in all flip-flops simultaneously
Loading data in two of the flip-flops
Loading data in all four flip-flops at the same time
Momentarily disabling the synchronous SET and RESET inputs
Loading data in all four flip-flops at the same time
49
What is a shift register that will accept a parallel input and can shift data left or right called?
tri-state
end around
bidirectional universal
conversion
bidirectional universal
50
What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
The output word decreases by 1.
The output word decreases by 2.
The output word increases by 1.
The output word increases by 2.
The output word decreases by 1.
51
Mod-6 and mod-12 counters are most commonly used in:
frequency counters
multiplexed displays
digital clocks
power consumption meters
digital clocks
52
What are the two types of basic adder circuits?
half adder and full adder
half adder and parallel adder
asynchronous and synchronous
one's complement and two's complement
half adder and full adder
53
The fast carry or look-ahead carry circuits found in most 4-bit parallel-adder circuits:
increase ripple delay
add a 1 to complemented inputs
reduce propagation delay
determine sign and magnitude
reduce propagation delay
54
How many basic binary subtraction operations are possible?
4
3
2
1
1
55
How many basic binary subtraction combinations are possible?
4
3
2
1
4
56
The selector inputs to an arithmetic-logic unit (ALU) determine the:
selection of the IC
arithmetic or logic function
data word selection
clock frequency to be used
arithmetic or logic function
57
A computerized self-diagnostic for a ROM test uses:
the check-sum method
a ROM listing
ROM comparisons
a checkerboard test
the check-sum method
58
How many storage locations are available when a memory device has twelve address lines?
144
512
2048
4096
4096
59
Which of the following memories uses a MOSFET and a capacitor as its memory cell?
SRAM
DRAM
ROM
DROM
DRAM
60
Which of the following best describes nonvolatile memory?
memory that retains stored information when electrical power is removed
memory that loses stored information when electrical power is removed
magnetic memory
nonmagnetic memory
memory that retains stored information when electrical power is removed
61
The access time (tacc) of a memory IC is governed by the IC's:
internal address buffer
internal address decoder
volatility
internal address decoder and volatility
internal address decoder
62
Select the best description of read-only memory (ROM).
nonvolatile, used to store information that changes during system operation
nonvolatile, used to store information that does not change during system operation
volatile, used to store information that changes during system operation
volatile, used to store information that does not change during system operation
nonvolatile, used to store information that does not change during system operation
63
Advantage(s) of an EEPROM over an EPROM is (are):
the EPROM can be erased with ultraviolet light in much less time than an EEPROM
the EEPROM can be erased and reprogrammed without removal from the circuit
the EEPROM has the ability to erase and reprogram individual words
the EEPROM can erase and reprogram individual words without removal from the circuit
the EEPROM can erase and reprogram individual words without removal from the circuit
64
Which of the following RAM timing parameters determine(s) its operating speed?
tacc
taa and tacs
t1 and t3
trc and twc
t1 and t3
65
Memory that loses its contents when power is lost is:
nonvolatile
volatile
random
static
Volatile
66
Select the best description of the fusible-link PROM.
user programmable, one-time programmable
manufacturer programmable, one-time programmable
user programmable, reprogrammable
manufacturer programmable, reprogrammable
user programmable, one-time programmable
67
A nonvolatile type of memory that can be programmed and erased in sectors, rather than one byte at a time is:
flash memory
EPROM
EEPROM
MPROM
flash memory
68
Which of the following best describes static memory devices?
memory devices that are magnetic in nature and do not require constant refreshing
semiconductor memory devices in which stored data is retained as long as power is applied
memory devices that are magnetic in nature and require constant refreshing
semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed
semiconductor memory devices in which stored data is retained as long as power is applied
69
What is the principal advantage of using address multiplexing with DRAM memory?
reduced memory access time
reduced requirement for constant refreshing of the memory contents
reduced pin count and decrease in package size
no requirement for a chip-select input line, thereby reducing the pin count
reduced pin count and decrease in package size
70
Which of the following is a type of error associated with digital-to-analog converters (DACs)?
nonmonotonic error
incorrect output codes
offset error
nonmonotonic and offset error
nonmonotonic and offset error
71
A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the analog output for the input code 0101.
0.3125 V
3.125 V
0.78125 V
–3.125 V
3.125 V
72
What is the resolution of a digital-to-analog converter (DAC)?
It is the comparison between the actual output of the converter and its expected output.
It is the deviation between the ideal straight-line output and the actual output of the converter.
It is the smallest analog output change that can occur as a result of an increment in the digital input.
It is its ability to resolve between forward and reverse steps when sequenced over its entire range.
It is the smallest analog output change that can occur as a result of an increment in the digital input.
73
The practical use of binary-weighted digital-to-analog converters is limited to:
R/2R ladder D/A converters
4-bit D/A converters
8-bit D/A converters
op-amp comparators
4-bit D/A converters
74
The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the:
quantization
accuracy
resolution
monotonicity
resolution
75
The primary disadvantage of the flash analog-to digital converter (ADC) is that:
it requires the input voltage to be applied to the inputs simultaneously
a long conversion time is required
a large number of output lines is required to simultaneously decode the input voltage
a large number of comparators is required to represent a reasonable sized binary number
a large number of comparators is required to represent a reasonable sized binary number
76
What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted digital-to-analog DAC converter?
It only uses two different resistor values.
It has fewer parts for the same number of inputs.
Its operation is much easier to analyze.
The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot.
It only uses two different resistor values.
77
The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is:
63%
64%
1.56%
15.6%
1.56%
78
In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:
decoder
priority encoder
multiplexer
demultiplexer
priority encoder
79
Which is not an analog-to-digital (ADC) conversion error?
differential nonlinearity
missing code
incorrect code
offset
differential nonlinearity
80
Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:
sample and hold the output of the binary counter during the conversion process
stabilize the comparator's threshold voltage during the conversion process
stabilize the input analog signal during the conversion process
sample and hold the D/A converter staircase waveform during the conversion process
stabilize the input analog signal during the conversion process
81
When referring to instruction words, a mnemonic is:
a short abbreviation for the operand address
a short abbreviation for the operation to be performed
a short abbreviation for the data word stored at the operand address
shorthand for machine language
a short abbreviation for the operation to be performed
82
What is the difference between mnemonic codes and machine codes?
There is no difference.
Machine codes are in binary, mnemonic codes are in shorthand English.
Machine codes are in shorthand English, mnemonic codes are in binary.
Machine codes are in shorthand English, mnemonic codes are a high-level language.
Machine codes are in binary, mnemonic codes are in shorthand English.
83
Which bus is bidirectional?
data bus
control bus
address bus
multiplexed bus
data bus
84
The software used to drive microprocessor-based systems is called:
assembly language programs
firmware
BASIC interpreter instructions
flowchart instructions
assembly language programs
85
A microprocessor unit, a memory unit, and an input/output unit form a:
CPU
compiler
microcomputer
ALU
microcomputer
86
How many buses are connected as part of the 8085 microprocessor?
2
3
5
8
3
87
Which of the following is not a computer bus?
data bus
timer bus
control bus
address bus
timer bus
88
The technique of assigning a memory address to each I/O device in the SAM system is called:
wired I/O
I/O mapping
dedicated I/O
memory-mapped I/O
memory-mapped I/O
89
How many bits are used in the data bus?
7
8
9
16
8
90
A port can be:
strictly for input
strictly for output
bidirectional
all the above
bidirectional
91
Which of the following is not a basic element within the microprocessor?
microcontroller
arithmetic-logic unit (ALU)
temporary register
accumulator
microcontroller
92
How many bits are used in the address bus?
7
8
9
16
16
93
Exceptions to the 8085 microprocessor normal operation are called:
jump instructions
decoding
interrupts
jump instructions or interrupts
jump instructions or interrupts
94
A digital logic device used as a buffer should have what input/output characteristics?
high input impedance and high output impedance
low input impedance and high output impedance
low input impedance and low output impedance
high input impedance and low output impedance
high input impedance and low output impedance
95
What is the standard TTL noise margin?
5.0 V
0.2 V
0.8 V
0.4 V
0.4 V
96
The range of a valid LOW input is:
0.0 V to 0.4 V
0.4 V to 0.8 V
0.4 V to 1.8 V
0.4 V to 2.4 V
0.4 V to 0.8 V
97
When an IC has two rows of parallel connecting pins, the device is referred to as:
a QFP
a DIP
a phase splitter
CMOS
DIP
98
Which digital IC package type makes the most efficient use of printed circuit board space?
SMT
TO can
flat pack
DIP
SMT
99
The problem of interfacing IC logic families that have different supply voltages (VCCs) can be solved by using a:
level-shifter
tri-state shifter
translator
level-shifter or translator
level-shifter or translator
100
Ten TTL loads per TTL driver is known as:
noise immunity
power dissipation
fanout
propagation delay
fanout
101
Which of the following summarizes the important features of emitter-coupled logic (ECL)?
negative voltage operation, high speed, and high power consumption
good noise immunity, negative logic, high frequency capability, low power dissipation, and short propagation time
slow propagation time, high frequency response, low power consumption, and high output voltage swings
poor noise immunity, positive supply voltage operation, good low-frequency operation, and low power
negative voltage operation, high speed, and high power consumption
102
What quantities must be compatible when interfacing two different logic families?
only the currents
both the voltages and the currents
only the voltages
both the power dissipation and the impedance
both the voltages and the currents
103
CMOS logic is probably the best all-around circuitry because of its:
packing density
low power consumption
very high noise immunity
low power consumption and very high noise immunity
low power consumption and very high noise immunity
104
Low power consumption achieved by CMOS circuits is due to which construction characteristic?
complementary pairs
connecting pads
DIP packages
small-scale integration
complementary pairs
105
A TTL totem pole circuit is designed so that the output transistors are:
always on together
providing phase splitting
providing voltage regulation
never on together
never on together
106
The time needed for an output to change as the result of an input change is known as:
noise immunity
fanout
propagation delay
rise time
propagation delay
107
Which type of PLD should be used to program basic logic functions?
PLA
PAL
CPLD
SLD
PAL
108
The content of a simple programmable logic device (PLD) consists of:
fuse-link arrays
thousands of basic logic gates
advanced sequential logic functions
thousands of basic logic gates and advanced sequential logic functions
thousands of basic logic gates and advanced sequential logic functions
109
Once a PAL has been programmed:
it cannot be reprogrammed.
its outputs are only active HIGHs
its outputs are only active LOWs
its logic capacity is lost
it cannot be reprogrammed.
110
The complex programmable logic device (CPLD) contains several PLD blocks and:
field-programmable switches
AND/OR arrays
a global interconnection matrix
a language compiler
a global interconnection matrix
111
PLAs, CPLDs, and FPGAs are all which type of device?
SLD
PLD
EPROM
SRAM
PLD
112
The difference between a PLA and a PAL is:
the PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane
the PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane
the PAL has more possible product terms than the PLA
PALs and PLAs are the same thing.
the PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane
113
A series of gradually decreasing sine wave oscillations is called:
ringing
slew
overshooting
undershooting
ringing
114
The determination of a digital signal's frequency and waveshape is best accomplished with which test equipment?
an oscilloscope
a multimeter
a spectrum analyzer
a frequency generator
an oscilloscope
115
A logic probe is placed on the output of a gate and the display indicator is dim. A logic pulser is used on each of the input terminals, but the output indication does not change. What is wrong?
The dim indication on the logic probe indicates that the supply voltage is probably low.
The output of the gate appears to be open.
The LOW indication is the result of a bad ground connection on the logic probe.
The gate is a tri-state device
The output of the gate appears to be open.
116
A +5 V PCB power source that has been "pulled down" to a +3.4 V level may be due to:
a circuit open
a faulty regulator
the half-split method
a circuit short
a circuit short
117
Measurement of pulse width should be taken at a 50% mean of the:
overshoot and undershoot
rise and fall
damping and ringing
leading and trailing amplitude
rise and fall
118
Which test equipment best allows a comparison between input and output signals?
an oscilloscope
a logic probe
a spectrum analyzer
a multitrace oscilloscope
a multitrace oscilloscope
119
What is the next step after discovering a faulty gate within an IC?
repair the gate
resolder the tracks
replace the IC involved
recheck the power source
replace the IC involved
120
The use of a multimeter with digital circuits allows the measurement of:
pulse width
voltage or resistance
current
pulse trains
voltage or resistance
121
The use of triggered sweep when using an oscilloscope provides more accuracy in which area?
frequency
amplitude
graticule activity
timing
timing
122
IThe time needed for a pulse to increase from 10% to 90% of its amplitude defines:
pulse width
propagation delay
rise time
duty cycle
rise time
123
The time needed for a pulse to increase from 10% to 90% of its amplitude defines:
pulse width
propagation delay
rise time
duty cycle
rise time
