micro, comp & memory Flashcards
(151 cards)
1
Q
The devices that provide the means for a computer to communicate with the user or other computers are referred to as:
CPU
ALU
I/O
none of the above
A
I/O
2
Q
The software used to drive microprocessor-based systems is called:
assembly language
firmware
machine language code
BASIC interpreter instructions
A
assembly language
3
Q
The circuits in the 8085A that provide the arithmetic and logic functions are called the:
CPU
ALU
I/O
none of the above
A
ALU
4
Q
How many buses are connected as part of the 8085A microprocessor?
2
3
5
8
A
3
5
Q
The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.
control bus
control instructions
address decoder
CPU
A
address decoder
6
Q
How many bits are used in the data bus?
7
8
9
16
A
8
7
Q
The items that you can physically touch in a computer system are called:
software
firmware
hardware
none of the above
A
hardware
8
Q
Single-bit indicators that may be set or cleared to show the results of logical or arithmetic operations are the:
flags
registers
monitors
decisions
A
flags
9
Q
When referring to instruction words, a mnemonic is:
a short abbreviation for the operand address
a short abbreviation for the operation to be performed
a short abbreviation for the data word stored at the operand address
shorthand for machine language
A
a short abbreviation for the operation to be performed
10
Q
The technique of assigning a memory address to each I/O device in the computer system is called:
memory-mapped I/O
ported I/O
dedicated I/O
wired I/O
A
memory-mapped I/O
11
Q
When was the first 8-bit microprocessor introduced?
1969
1974
1979
1985
A
1974
12
Q
What type of circuit is used at the interface point of an output port?
decoder
latch
tristate buffer
none of the above
A
latch
13
Q
I/O mapped systems identify their input/output devices by giving them a(n) ________.
8-bit port number
16-bit port number
8-bit buffer number
8-bit instruction
A
8-bit port number
14
Q
What type of circuit is used at the interface point of an input port?
decoder
latch
tristate buffer
none of the above
A
tristate buffer
15
Q
The register in the 8085A that is used to keep track of the memory address of the next op-code to be run in the program is the:
stack pointer
program counter
instruction pointer
accumulator
A
program counter
16
Q
All computer programs for a machine are called:
software
firmware
hardware
none of the above
A
software
17
Q
The 8085A is a(n):
16-bit parallel CPU
8-bit serial CPU
8-bit parallel CPU
none of the above
A
8-bit parallel CPU
18
Q
Because microprocessor CPUs do not understand mnemonics as they are, they have to be converted to ________.
hexadecimal machine code
binary machine code
assembly language
all of the above
A
binary machine code
19
Q
A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic operation is the:
stack pointer
program counter
instruction pointer
accumulator
A
accumulator
20
Q
What is the difference between a mnemonic code and machine code?
There is no difference.
Machine codes are in binary, mnemonic codes are in shorthand English.
Machine codes are in shorthand English, mnemonic codes are in binary.
A
Machine codes are in binary, mnemonic codes are in shorthand English.
21
Q
Which bus is a bidirectional bus?
address bus
data bus
address bus and data bus
none of the above
A
data bus
22
Q
Which of the following buses is primarily used to carry signals that direct other ICs to find out what type of operation is being performed?
data bus
control bus
address bus
address decoder bus
A
control bus
23
Q
What kind of computer program is used to convert mnemonic code to machine code?
debug
assembler
C++
Fortran
A
assembler
24
Q
Which of the following are the three basic sections of a microprocessor unit?
operand, register, and arithmetic/logic unit (ALU)
control and timing, register, and arithmetic/logic unit (ALU)
control and timing, register, and memory
arithmetic/logic unit (ALU), memory, and input/output
A
control and timing, register, and arithmetic/logic unit (ALU)
25
Which of the following is not a basic element within the microprocessor?
Microcontroller
Arithmetic logic unit (ALU)
Register array
Control unit
Microcontroller
26
Which method bypasses the CPU for certain types of data transfer?
Software interrupts
Interrupt-driven I/O
Polled I/O
Direct memory access (DMA)
Direct memory access (DMA)
27
Which of the following is not an enhancement to the Pentium that was unavailable in the 8086/8088?
"Pipelined" architecture
Expansion of cache memory
Inclusion of an internal math coprocessor
Data/address line multiplexing
Data/address line multiplexing
28
Which bus is bidirectional?
Address bus
Control bus
Data bus
None of the above
Data bus
29
DMA is particularly suited for data transfer between the ________.
disk drive and CPU
disk drive and RAM
disk drive and ROM
disk drive and I/O
disk drive and RAM
30
The first microprocessor had a(n)________.
1-bit data bus
2-bit data bus
4-bit data bus
8-bit data bus
4-bit data bus
31
Which microprocessor has multiplexed data and address lines?
8086/8088
80286
80386
Pentium
8086/8088
32
Which is not an operand?
Variable
Register
Memory location
Assembler
Assembler
33
Which is not part of the execution unit (EU)?
Arithmetic logic unit (ALU)
Clock
General registers
Flags
Clock
34
A 20-bit address bus can locate ________.
1,048,576 locations
2,097,152 locations
4,194,304 locations
8,388,608 locations
1,048,576 locations
35
What is occurring when two or more sources of data attempt to use the same bus?
Bus contention
Direct memory access
Bus interruption
PPI
Bus contention
36
Which of the following is not a jump instruction?
JB (jump back)
JA (jump above)
JO (jump if overflow)
JMP (unconditional jump)
JB (jump back)
37
Which of the following was not a design improvement for the 8086/8088 over the 8085?
Execution unit (EU)
16-bit data bus
Arithmetic logic unit (ALU)
Bus interface unit (BIU)
Arithmetic logic unit (ALU)
38
Polled I/O works best when ________.
there are no priority considerations
priority considerations are frequent
the polling rate exceeds 1000 s
the polling rate is below 1000 s
there are no priority considerations
39
Which of the following is not an arithmetic instruction?
INC (increment)
CMP (compare)
DEC (decrement)
ROL (rotate left)
ROL (rotate left)
40
During a read operation the CPU fetches ________.
a program instruction
another address
data itself
all of the above
all of the above
41
The first Intel microprocessor to contain on-board cache memory was the ________.
80386
80486
Pentium
Pentium Pro
80486
42
Which of the following is not an 8086/8088 general-purpose register?
Code segment (CS)
Data segment (DS)
Stack segment (SS)
Address segment (AS)
Address segment (AS)
43
Which of the following is not a computer bus?
Data bus
Control bus
Timer bus
Address bus
Timer bus
44
With interrupt-driven I/O, if two or more devices request service at the same time, ________.
the device closest to the CPU gets priority
the device that is fastest gets priority
the device assigned the highest priority is serviced first
the system is likely to crash
the device that is fastest gets priority
45
The Pentium can address ________.
1 MB
1 GB
2 GB
4 GB
4Gb
46
A port can be ________.
strictly for input
strictly for output
bidirectional
all of the above
bidirectional
47
Which of the following is not a computer functional block?
Analog-to-digital converter
Central-processing unit
Memory
Input/output ports
Analog-to-digital converter
48
The Pentium microprocessor has a data bus of ________.
16 bits
32 bits
64 bits
128 bits
64 bits
49
The process of jointly establishing communication is called ________.
DMA
bidirectional addressing
multiplexing
handshaking
handshaking
50
The internal RAM memory of the 8051 is:
32 bytes
64 bytes
128 bytes
256 bytes
128 bytes
51
The 8051 has ________ 16-bit counter/timers.
1
2
3
4
2
52
The 8051 can handle ________ interrupt sources.
3
4
5
6
5
53
When the 8051 is reset and the EA' line is HIGH, the program counter points to the first program instruction in the:
internal code memory
external code memory
internal data memory
external data memory
internal code memory
54
An alternate function of port pin P3.4 in the 8051 is:
Timer 0
Timer 1
interrupt 0
interrupt 1
Timer 0
55
The I/O ports that are used as address and data for external memory are:
ports 1 and 2
ports 1 and 3
ports 0 and 2
ports 0 and 3
ports 0 and 2
56
Microcontrollers often have:
CPUs
RAM
ROM
all of the above
all of the above
57
The 8051 has ________ parallel I/O ports.
2
3
4
5
4
58
The total external data memory that can be interfaced to the 8051 is:
32K
64K
128K
256K
64K
59
Bit-addressable memory locations are:
10H through 1FH
20H through 2FH
30H through 3FH
40H through 4FH
20H through 2FH
60
The 8-bit address bus allows access to an address range of:
0000 to FFFFH
000 to FFFH
00 to FFH
0 to FH
00 to FFH
61
The start-conversion on the ADC0804 is done by using the:
SC'
CS line
INTR line
V ref/2 line
SC'
62
The number of data registers is:
8
16
32
64
32
63
When the 8051 is reset and the EA line is LOW, the program counter points to the first program instruction in the:
internal code memory
external code memory
internal data memory
external data memory
external code memory
64
What is the difference between the 8031 and the 8051?
The 8031 has no interrupts.
The 8031 is ROM-less.
The 8051 is ROM-less.
The 8051 has 64 bytes more memory.
The 8031 is ROM-less
65
The I/O port that does not have a dual-purpose role is:
port 0
port 1
port 2
port 3
port 1
66
The total amount of external code memory that can be interfaced to the 8051 is:
32K
64K
128K
256K
64K
67
The ADC0804 has ________ resolution.
4-bit
8-bit
16-bit
32-bit
8-bit
68
A HIGH on which pin resets the 8051 microcontroller?
RESET
RST
PSEN
RSET
RST
69
An alternate function of port pin P3.1 in the 8051 is:
serial port input
serial port output
memory write strobe
memory read strobe
serial port output
70
An alternate function of port pin P3.0 (RXD) in the 8051 is:
serial port input
serial port output
memory write strobe
memory read strobe
serial port input
71
How many address bits are needed to select all memory locations in the 2118 16K × 1 RAM?
8
10
14
16
14
72
The check sum method of testing a ROM:
indicates if the data in more than one memory location is incorrect.
provides a means for locating and correcting data errors in specific memory locations.
allows data errors to be pinpointed to a specific memory location.
simply indicates that the contents of the ROM are incorrect.
simply indicates that the contents of the ROM are incorrect.
73
What is the meaning of RAM, and what is its primary role?
Readily Available Memory; it is the first level of memory used by the computer in all of its operations.
Random Access Memory; it is memory that can be reached by any sub- system within a computer, and at any time.
Random Access Memory; it is the memory used for short-term temporary data storage within the computer.
Resettable Automatic Memory; it is memory that can be used and then automatically reset, or cleared, after being read from or written to.
Random Access Memory; it is the memory used for short-term temporary data storage within the computer.
74
The storage element for a static RAM is the ________.
diode
resistor
capacitor
flip-flop
flip-flop
75
In a DRAM, what is the state of R/W during a read operation?
Low
High
Hi-Z
None of the above
High
76
The condition occurring when two or more devices try to write data to a bus simultaneously is called ________.
address decoding
bus contention
bus collisions
address multiplexing
bus contention
77
Which is/are the basic refresh mode(s) for dynamic RAM?
Burst refresh
Distributed refresh
Open refresh
Burst refresh and distributed refresh
Burst refresh and distributed refresh
78
One of the most important specifications on magnetic media is the ________.
rotation speed
tracks per inch
data transfer rate
polarity reversal rate
data transfer rate
79
A 64-bit word consists of ________.
4 bytes
8 bytes
10 bytes
12 bytes
8 bytes
80
Which of the following RAM timing parameters determine its operating speed?
tACC
tAA and tACS
tCO and tOD
tRC and tWC
tRC and tWC
81
The reason the data outputs of most ROM ICs are tristate outputs is to:
allow for three separate data input lines.
allow the bidirectional flow of data between the bus lines and the ROM registers.
permit the connection of many ROM chips to a common data bus.
isolate the registers from the data bus during read operations.
permit the connection of many ROM chips to a common data bus.
82
Select the statement that best describes Read-Only Memory (ROM).
nonvolatile, used to store information that changes during system operation
nonvolatile, used to store information that does not change during system operation
volatile, used to store information that changes during system operation
volatile, used to store information that does not change during system operation
nonvolatile, used to store information that does not change during system operation
83
How many 2K × 8 ROM chips would be required to build a 16K × 8 memory system?
2
4
8
16
8
84
What is the maximum time required before a dynamic RAM must be refreshed?
2 ms
4 ms
8 ms
10 ms
2ms
85
Which of the following best describes random-access memory (RAM)?
a type of memory in which access time depends on memory location
a type of memory that can be written to only once but can be read from an infinite number of times
a type of memory in which access time is the same for each memory location
mass memory
a type of memory in which access time is the same for each memory location
86
Which of the following best describes static memory devices?
memory devices that are magnetic in nature and do not require constant refreshing
memory devices that are magnetic in nature and require constant refreshing
semiconductor memory devices in which stored data will not be retained with the power applied unless constantly refreshed
semiconductor memory devices in which stored data is retained as long as power is applied
semiconductor memory devices in which stored data is retained as long as power is applied
87
Which is not a removable drive?
Zip
Jaz
Hard
SuperDisk
Hard
88
Which of the following best describes EPROMs?
EPROMs can be programmed only once.
EPROMs can be erased by UV.
EPROMs can be erased by shorting all inputs to the ground.
All of the above.
EPROMs can be erased by UV.
89
How many storage locations are available when a memory device has 12 address lines?
144
512
2048
4096
4096
90
FIFO is formed by an arrangement of ________.
diodes
transistors
MOS cells
shift registers
shift registers
91
Why do most dynamic RAMs use a multiplexed address bus?
It is the only way to do it.
to make it faster
to keep the number of pins on the chip to a minimum
to keep the number of pins on the chip to a minimum
92
CCD stands for ________.
capacitor charging device
capacitor-capacitor drain
charged-capacitor device
charge-coupled device
charge-coupled device
93
What is the major difference between SRAM and DRAM?
DRAMs must be periodically refreshed.
SRAMs can hold data via a static charge, even with power off.
The only difference is the terminal from which the data is removed—from the FET Drain or Source.
Dynamic RAMs are always active; static RAMs must reset between data read/write cycles.
DRAMs must be periodically refreshed.
94
Which of the following best describes volatile memory?
memory that retains stored information when electrical power is removed
memory that loses stored information when electrical power is removed
magnetic memory
nonmagnetic
memory that loses stored information when electrical power is removed
95
What is a major disadvantage of RAM?
Its access speed is too slow.
Its matrix size is too big.
It is volatile.
High power consumption
It is volatile
96
What two functions does a DRAM controller perform?
address multiplexing and data selection
address multiplexing and the refresh operation
data selection and the refresh operation
data selection and CPU accessing
address multiplexing and the refresh operation
97
Dynamic memory cells store a data bit in a ________.
diode
resistor
capacitor
flip-flop
capacitor
98
Which is not part of a hard disk drive?
Spindle
Platter
Read/write head
Valve
Valve
99
ROMs retain data when the ________.
power is off
power is on
system is down
all of the above
all of the above
100
Typically, how often is DRAM refreshed?
2 to 8 ms
4 to 16 ms
8 to 16us
1 to 2us
4 to 16 ms
101
Which type of ROM can be erased by an electrical signal?
ROM
mask ROM
EPROM
EEPROM
EEPROM
102
Data is written to and read from the disk via a magnetic ________ head mechanism in the floppy drive.
cylinder
read/write
recordable
cluster
read/write
103
How many address lines would be required for a 2K × 4 memory chip?
8
10
11
12
11
104
When a RAM module passes the checkerboard test it is:
able to read and write only 1s.
faulty.
probably good.
able to read and write only 0s.
probably good
105
Which type of ROM has to be custom built by the factory?
ROM
mask ROM
EPROM
EEPROM
mask ROM
106
What is the computer main memory?
Hard drive and RAM
CD-ROM and hard drive
RAM and ROM
CMOS and hard drive
RAM and ROM
107
A major disadvantage of the mask ROM is that it:
is time consuming to change the stored data when system requirements change
is very expensive to change the stored data when system requirements change
cannot be reprogrammed if stored data needs to be changed
has an extremely short life expectancy and requires frequent replacement
cannot be reprogrammed if stored data needs to be changed
108
The periodic recharging of DRAM memory cells is called ________.
multiplexing
bootstrapping
refreshing
flashing
refreshing
109
Which of the following is normally used to initialize a computer system's hardware?
Bootstrap memory
Volatile memory
External mass memory
Static memory
Bootstrap memory
110
What is the difference between static RAM and dynamic RAM?
Static RAM must be refreshed, dynamic RAM does not.
There is no difference.
Dynamic RAM must be refreshed, static RAM does not.
Dynamic RAM must be refreshed, static RAM does not
111
Microprocessors and memory ICs are generally designed to drive only a single TTL load. Therefore, if several inputs are being driven from the same bus, any memory IC must be ________.
buffered
decoded
addressed
stored
buffered
112
Which type of ROM can be erased by UV light?
ROM
mask ROM
EPROM
EEPROM
EPROM
113
Which of the following is NOT a type of memory?
RAM
ROM
FPROM
EEPROM
FPROM
114
How many address bits are required for a 4096-bit memory organized as a 512 × 8 memory?
2
4
8
9
9
115
In general, the ________ have the smallest bit size and the ________ have the largest.
EEPROMs, Flash
SRAM, mask ROM
mask ROM, SRAM
DRAM, PROM
EEPROMs, Flash
116
Advantage(s) of an EEPROM over an EPROM is/are:
the EPROM can be erased with ultraviolet light in much less time than an EEPROM
the EEPROM can be erased and reprogrammed without removal from the circuit
the EEPROM has the ability to erase and reprogram individual words
the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words
the EEPROM can be erased and reprogrammed without removal from the circuit, and can erase and reprogram individual words
117
The mask ROM is ________.
permanently programmed during the manufacturing process
volatile
easy to reprogram
extremely expensive
permanently programmed during the manufacturing process
118
How many 1K × 4 RAM chips would be required to build a 1K × 8 memory system?
2
4
8
16
2
119
Which of the following memories uses a MOS capacitor as its memory cell?
SRAM
DRAM
ROM
FIFO
DRAM
120
Which of the following faults will the checkerboard pattern test for in RAM?
Short between adjacent cells
Ability to store both 0s and 1s
Dynamically introduced errors between cells
All of the above
All of the above
121
On a CD-ROM, ________ are raised areas representing a 1.
mounds
lands
holes
pits
lands
122
The location of a unit of data in a memory array is called its ________.
storage
RAM
address
data
address
123
On a CD-ROM, ________ are recessed areas representing a 0.
mounds
lands
holes
pits
pits
124
Why is a refresh cycle necessary for a dynamic RAM?
to clear the flip-flops
to set the flip-flops
The refresh cycle discharges the capacitor cells.
The refresh cycle keeps the charge on the capacitor cells.
The refresh cycle keeps the charge on the capacitor cells.
125
Which is not a magnetic storage device?
Magnetic disk
Magnetic tape
Magneto-optical disk
Optical disk
Optical disk
126
The time from the beginning of a read cycle to the end of tACS or tAA is referred to as:
access time
data hold
read cycle time
write enable time
access time
127
Which of the following memories is volatile?
ROM
EROM
RAM
Flash
RAM
128
The refresh period for capacitors used in DRAMs is ________.
2 ms
2 s
64 ms
64 s
2ms
129
What is the principal advantage of using address multiplexing with DRAM memory?
reduced memory access time
reduced requirement for constant refreshing of the memory contents
reduced pin count and decrease in package size
It eliminates the requirement for a chip-select input line, thereby reducing the pin count.
reduced pin count and decrease in package size
130
What is a multitap digital delay line?
a series of inverter gates with RC circuits between each one
a series of inverter gates with RL circuits between each one
a series of NAND gates with RC circuits between each one
a series of NAND gates with RL circuits between each one
a series of inverter gates with RC circuits between each one
131
The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ________.
4096
8129
16358
32768
16358
132
How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
Eight
Four
Two
One
Eight
133
The mask ROM is ________.
MOS technology
diode technology
resistor-diode technology
DROM technology
MOS technology
134
Which of the following is not a flash memory mode or operation?
Burst
Read
Erase
Programming
Burst
135
The smallest unit of binary data is the ________.
bit
nibble
byte
word
bit
136
Select the statement that best describes the fusible-link PROM.
user-programmable, one-time programmable
manufacturer-programmable, one-time programmable
user-programmable, reprogrammable
manufacturer-programmable, reprogrammable
user-programmable, one-time programmable
137
How can UV erasable PROMs be recognized?
There is a small window on the chip.
They will have a small violet dot next to the #1 pin.
Their part number always starts with a "U", such as in U12.
They are not readily identifiable, since they must always be kept under a small cover.
There is a small window on the chip.
138
What part of a Flash memory architecture manages all chip functions?
I/O pins
floating-gate MOSFET
command code
program verify code
floating-gate MOSFET
139
An 8-bit address code can select ________.
8 locations in memory
256 locations in memory
65,536 locations in memory
131,072 locations in memory
256 locations in memory
140
Eight bits of digital data are normally referred to as a:
group.
byte.
word.
cell.
byte
141
Which is not a hard disk performance parameter?
Seek time
Break time
Latency period
Access time
Break time
142
The ideal memory ________.
has high storage capacity
is nonvolatile
has in-system read and write capacity
has all of the above characteristics
has all of the above characteristics
143
To which pin on the RAM chip does the address decoder connect in order to signal which memory chip is being accessed?
The address input
The output enable
The chip enable
The data input
The chip enable
144
EEPROM stands for ________.
encapsulated electrical programmable read-only memory
elementary electrical programmable read-only memory
electrically erasable programmable read-only memory
elementary erasable programmable read-only memory
electrically erasable programmable read-only memory
145
L1 is known as ________.
primary cache
secondary cache
DRAM
SRAM
primary cache
146
Describe the timing diagram of a write operation.
First the data is set on the data bus and the address is set, then the write pulse stores the data.
First the address is set, then the data is set on the data bus, and finally the read pulse stores the data.
First the write pulse stores the data, then the address is set, and finally the data is set on the data bus.
First the data is set on the data bus, then the write pulse stores the data, and finally the address is set.
First the data is set on the data bus and the address is set, then the write pulse stores the data.
147
What is the bit storage capacity of a ROM with a 1024 × 8 organization?
1024
2048
4096
8192
8192
148
Which of the following is one of the basic characteristics of DRAMs?
DRAMs must have a constantly changing input.
DRAMs must be periodically refreshed in order to be able to retain data.
DRAMs have a broader "dynamic" storage range than other types of memories.
DRAMs are simpler devices than other types of memories.
DRAMs must be periodically refreshed in order to be able to retain data.
149
The main advantage of semiconductor RAM is its ability to:
retain stored data when power is interrupted or turned off
be written to and read from rapidly
be randomly accessed
be sequentially accessed
be written to and read from rapidly
150
Which of the following describes the action of storing a bit of data in a mask ROM?
A 1 is stored in a bipolar cell by opening the base connection to the address line.
A 0 is stored in a bipolar cell by shorting the base connection to the address line.
A 1 is stored by connecting the gate of a MOS cell to the address line.
A 0 is stored by connecting the gate of a MOS cell to the address line.
A 1 is stored by connecting the gate of a MOS cell to the address line.
151
Address decoding for dynamic memory chip control may also be used for:
controlling refresh circuits
read and write control
chip selection and address location
memory mapping
chip selection and address location
