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Embedded Software > Bus-Based Computer Systems > Flashcards

Bus-Based Computer Systems Flashcards

1
Q

What is the function of a CPU bus?

A

allows memory, CPU, and devices to communicate

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2
Q

What is a bus?

A

a set of wires/communication protocol

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3
Q

What determines how devices communicate?

A

bus protocol

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4
Q

What happens to devices on the bus?

A

they go through a sequence of states

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5
Q

What are protocols specified by?

A

state machines

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6
Q

How many state machines per actor are there in the protocol?

A

one

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7
Q

Can bus protocols contain asynchronous logic?

A

yes

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8
Q

What are the steps of the four-cycle handshake?

A

dev 1 raises enquiry, dev 2 responds with acknowledgment, device 2 lowers acknowledgment once it is done, device 1 lowers enquiry

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9
Q

What provides synchronization in microprocessor busses?

A

the clock

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10
Q

R/W bit is true during what action?

A

reading

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11
Q

What is the name of the signal for when the data is ready?

A

Data ready bit

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12
Q

Address and data are how many lines?

A

a or n bit bundles of address and data lines (respectively)

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13
Q

How is the behavior of a bus most often specified?

A

a timing diagram

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14
Q

What are shown on timing diagrams to make sure signals go to the proper values at the proper times?

A

timing constraints

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15
Q

What must be provided when the data is ready?

A

Acknowledge

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16
Q

What does the data ready signal allow for?

A

the bus to be connected to devices that are slower than the bus

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17
Q

What is the wait state?

A

the cycles between the minimum time at which data can be asserted and when it is actually asserted

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18
Q

What is the wait state used for?

A

to connect slow, inexpensive memories to buses

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19
Q

What is DMA?

A

direct memory access which performs data transfers without executing instructions

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20
Q

What device sets up a data transfer?

A

the CPU

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21
Q

What does the DMA engine do during a data transfer?

A

fetches and writes data

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22
Q

What is a bus master by default?

A

CPU, sets up transfers

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23
Q

What must the DMA do to perform its work?

A

become the bus master

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24
Q

What is the bus mastership protocol?

A

bus request (DMA controller->CPU) then bus grant (CPU->DMA controller)

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25
Q

What is the operation of the DMA?

A

CPU sets DMA registers for start address and length, status register controls the unit, once DMA is bus master, transfers automatically

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26
Q

What do multiple busses allow for?

A

parallelism

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27
Q

What connects two busses?

A

a bridge

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28
Q

What are the two ARM AMBA bus varieties?

A

AHB and APB

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29
Q

What is the performance characteristic of the AHB bus variety?

A

high-performance

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30
Q

What are the cost/performance characteristics of the APB bus variety?

A

lower-speed, lower cost

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31
Q

What can the AHB bus variety support?

A

pipe-lining, burst transfers, split transactions, multiple bus masters

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32
Q

What is one of the key characteristics of the APB bus variety?

A

all devices are slaves

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33
Q

What types of memory is there?

A

DRAM, SRAM, and flash

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34
Q

What can vary with each type of memory?

A

capacity and width

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35
Q

What is DRAM?

A

dynamic random-access memory, requires refresh since the values inside the memory cells decay over time

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36
Q

What is SDRAM?

A

synchronous dynamic random-access memory, uses clock to improve performance and pipeline memory access

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37
Q

What are some current forms of SDRAM?

A

DDR (double-data rate) like DDR2 or DDR3

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38
Q

What is the dominant type of DRAM?

A

SDRAM

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39
Q

What is ROM?

A

Read only memory

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40
Q

What is a dominant form of field programmable ROM?

A

flash

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41
Q

True or false: ROM can only be field-programmable?

A

false, can be programmed at factory as well

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42
Q

What are some characteristics of flash?

A

electrically erasable, must be block erased, random access, but write/erase is much slower than read

43
Q

What is the flexible type of flash?

A

NOR

44
Q

What is the dense type of flash?

A

NAND

45
Q

True or false: flash memory is volatile?

A

false

46
Q

Can flash memory be programmed in circuit?

A

yes

47
Q

What is a negative about flash memory?

A

writing causes wear that eventually destroys the device, lifetime of approximately 1 mil writes

48
Q

What are the types of flash memory?

A

NAND and NOR

49
Q

Why is NAND the preferred type of flash?

A

cheaper, faster erase, and sequential access times

50
Q

What is the difference between a timer and a counter?

A

timer is incremented by a periodic signal and a counter is incremented by and async occasional signal

51
Q

What can cause interrupt with timers and counters?

A

rollover

52
Q

What is a watchdog timer?

A

a timer periodically reset by system timer

53
Q

What happens if a watchdog is not reset?

A

it generates an interrupt to reset the host

54
Q

How do you do digital to analog conversion?

A

use a resistor tree

55
Q

For an analog to digital conversion how many comparators do you need for N-bits?

A

2^n

56
Q

What is another way to convert from analog to digital?

A

dual-slope conversion

57
Q

How does dual-slope conversion eliminates non-linearities?

A

charging then discharging

58
Q

Why does a switch need to be debounced?

A

to eliminate mechanical bouncing

59
Q

How does an encoded keyboard work?

A

array of switches is read by an encoder, N-key rollover remembers multiple key depressions

60
Q

What must a LED use to limit current?

A

a resistor

61
Q

What kind of input can a 7-segment LCD display use?

A

parallel or multiplexed

62
Q

What is the dominant form of high-resolution displays?

A

LCD (liquid crystal display)

63
Q

What are some other types of high-resolution displays?

A

plasma, OLED

64
Q

What holds the current display contents in a display?

A

frame buffer

65
Q

What are display contents written and read by?

A

processor and video (respectively)

66
Q

What is the input device for a touchscreen?

A

two-dimensional voltmeter

67
Q

What are the two considerations for architecture?

A

software and hardware

68
Q

What are the considerations for hardware architecture design?

A

CPU, bus, memory, and I/O devices

69
Q

What are the considerations for software architecture design?

A

division among people, conceptual organization, performance, testability, maintenance

70
Q

Does the software design affect the hardware design and vice versa?

A

yes

71
Q

What are evaluation boards?

A

boards designed by CPU manufacturer that have CPU, memory and some I/O devices and often a prototyping section, can be used to start designing a custom board

72
Q

How can you add logic to a board?

A

PLDs, FPGAs, and ASICs

73
Q

What is the purpose of a PLD?

A

provides low/medium density logic

74
Q

What is the purpose of a FPGA?

A

provides more and higher-level logic

75
Q

What is the purpose of an ASIC?

A

(application-specific integrated circuit) made for a single purpose

76
Q

What is a platform?

A

the PC

77
Q

What are the advantages and disadvantages of a PC as a platform?

A

pros: cheap and easy to get, familiar software environment, cons: requires a lot of hardware resources, not well adapted to real time

78
Q

What are some typical busses in a PC?

A

PCI (peripheral component interconnect) and USB (universal serial bus)

79
Q

What are some software elements in a PC?

A

BIOS (low-level system software to implement low-level functions)

80
Q

What is the typical way for embedded software design?

A

host/target design

81
Q

What is host/target design?

A

use a host system to prepare software for target system

82
Q

What are some host-based tools?

A

cross compiler (compiles code on host for target), and cross debugger (displays target state and allows target to be controlled)

83
Q

What is a software debugger?

A

a monitor program residing on the target that provides basic debugger functions

84
Q

What do we need to be careful about with the program?

A

it should not destroy debugger program but should be able to recover some in case of damage caused by user code

85
Q

What is a breakpoint?

A

allows user to stop execution, examine state, and change state

86
Q

How does a breakpoint work from the instruction level?

A

replaces breakpointed instruction with a subroutine call to the monitor program

87
Q

What are the actions of the breakpoint handler?

A

save registers, allow user to examine machine, restore system state before returning

88
Q

What is the safest way to execute the breakpointed instruction?

A

replace it, execute in place, put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint

89
Q

What is an in-circuit emulator?

A

a specially-instrumented microprocessor that allows you to stop execution, examine CPU state, and modify registers

90
Q

What is a logic analyzer?

A

an array of low grade oscilloscopes

91
Q

What are the ways to exercise code?

A

run on: host, target, instruction-level simulator, cycle-accurate simulator, and hardware/software co-simulation environment

92
Q

What makes debugging difficult in real-time code?

A

bugs can cause non deterministic behavior and may be timing dependent

93
Q

Which elements does the performance depend on?

A

all: CPU, cache, bus, main memory, I/O device

94
Q

Which components does bandwidth apply to?

A

memory, bus, CPU fetches

95
Q

What is the bandwidth dependent on?

A

the clock rate and the width

96
Q

How do you increase the bandwidth?

A

increase width or clock rate

97
Q

How do you calculate the transfer time?

A

t (transfer time) = T (transfer cycles) * P (period of one cycle)

98
Q

How do you calculate transfer cycles?

A

Tbasic(N) = (D+O)*N/W (N=bytes to transfer W=bus width T=#of bus clock cycles P=bus clock period D=data transfer clock cycles O=overhead clock cycles)

99
Q

True or false: Memories of the same size always have the same aspect ratios.

A

false, can have different

100
Q

Where can you find the memory component access time?

A

chip data sheet

101
Q

What allow for faster access for successive transfers on the same page?

A

page modes

102
Q

What can speed things up?

A

parallelism

103
Q

When does DMA provide parallelism?

A

if the CPU doesn’t need the bus

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