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Instruction Sets and Processors Flashcards

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1
Q

What is the basic setup of von Neumann architecture?

A

memory and a CPU with registers for PC, IR, and general purpose registers

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2
Q

What is the basic setup of Harvard architecture?

A

data memory, program memory and a CPU with registers for PC, IR, and general purpose registers

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3
Q

What is the main difference between von Neumann and Harvard architectures?

A

harvard can’t use self-modifying code, von Neumann can, Harvard allows 2 simultaneous memory fetches, von Neumann doesn’t, Harvard has greater and more predictable memory bandwidth

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4
Q

What is RISC?

A

reduced instruction set computer, allows load/store, piplinable instructions

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5
Q

What is CISC?

A

complex instruction set computer, many addressing modes and operations

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6
Q

What are the characteristics of instruction sets?

A

fixed vs. variable length, addressing modes, number of operands, and types of operands

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7
Q

What is the programming model?

A

The registers visible to the programmer

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8
Q

What is an example of a register that is not visible to the programmer?

A

Instruction register (IR)

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9
Q

What are some characteristics that can vary between architecture implementations?

A

clock speeds, bus widths, cache sizes

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10
Q

True or false: all assembly languages are not one-to-one?

A

false

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11
Q

What are some basic features of an assembly language?

A

one instruction per line, labels provide names for addresses, instructions are in later columns, and columns run to end of line

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12
Q

What are pseudo-ops?

A

assembler directives that don’t correspond directly to instructions

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13
Q

What can pseudo ops usually do?

A

define current address, reserve storage, hold constants

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14
Q

True or false: there are many versions of the ARM architecture/assembly language?

A

true

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15
Q

What is the meaning if the N flag is logical one for both logical instructions and arithmetic instructions?

A

logical: no meaning, arithmetic: bit 31 is 1 meaning it is a neg number

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16
Q

What is the meaning if the Z flag is logical one for both logical instructions and arithmetic instructions?

A

logical: result is all zeroes, arithmetic: result of op was zero

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17
Q

What is the meaning if the C flag is logical one for both logical instructions and arithmetic instructions?

A

logical: after shift op, ‘1’ was left in carry flag, arithmetic: result is > 32 bits

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18
Q

What is the meaning if the V flag is logical one for both logical instructions and arithmetic instructions?

A

logical: no meaning, arithmetic: result is > 31 bits, possible corruption of signed bit

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19
Q

What is endianness?

A

relationship between bit and byte/word ordering

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20
Q

How is little endian set up?

A

Bit 31 is MSB, Byte 3 is MSByte

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21
Q

How is big endian set up?

A

Bit 31 is MSB, Byte 0 is MSByte

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22
Q

How big is a word in ARM?

A

32-bits

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23
Q

How many bytes can a word be divided into?

A

4 8-bit bytes

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24
Q

How long can ARM addresses be?

A

32-bits

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25
What does Address refer to?
byte
26
True or false: ARM is always big endian?
false, endianness can be set up at power-up
27
What does ADD/ADC do?
add/add with carry ex: ADD r0, r2, #3 (r0=r2+3)
28
What does SUB/SBC do?
subtract/subtract with carry ex: SUB r3, r4, r1 (r3=r4-r1)
29
What does RSB/RSC do?
reverse subtract/reverse subtract with carry ex: RSC r3, r4, r1 (r3=r1-r4)
30
What does MUL/MLA do?
multiply/multiply and accumulate ex: MUL r0, r1, r2, r3 (r0=r1*r2+r3)
31
What do AND, ORR, and EOR do?
bitwise AND, OR and XOR
32
What does BIC do?
bit clear
33
What does LSL/LSR do?
logical shift left/right (fills with zeroes) ex: LSL r0, r0, #10
34
What does ASL/ASR do?
arithmetic shift left/right (fills with ones) ex: ASR r0, r0, #10
35
What does ROR do?
rotate right ex: ROR r0, r0, #2
36
What does RRX do?
rotate right extended with C (33 bit rotate including the C bit) ex: RRX r0, r0
37
What does CMP do?
compare ex: CMP r1, #3 (does r1-3 and sets condition flags NZCV, does not save arithmetic result)
38
What does CMN do?
negated compare ex: CMN r1, #3 (does r1+3 and sets condition flags NZCV, does not save arithmetic result)
39
What does TST do?
bit-wise test (AND) (only sets NZCV flags doesn't save result) ex: TST r1, r2 (r1 & r2)
40
What does TEQ do?
bit-wise negated test (XOR) (only sets NZCV flags doesn't save result) ex: TEQ r1, r2 (r1 XOR r2)
41
What does MOV do?
move ex: MOV r1, r0 sets r1 to r0
42
What does MVN do?
bitwise NOT ex: MVN r0, r1 does a bitwise NOT of r1 and places it in r0
43
What do LDR, LDRH, and LDRB do?
load (half-word, byte) ex: LDR r0, [r1] loads the value stored at the memory address in r1 into r0
44
What do STR, STRH, and STRB do?
store (half-word, byte) ex: STR r0, [r1] storess the value in r0 to the memory location of the address stored in r1
45
True or false: You can refer to an address directly in an instruction.
false
46
What does ADR do?
retrieves the adress specified by the label and stores it in the register ex: ADR r0, FOO
47
What is the difference between ARM and C55x architecture?
ARM is load/store architecture, C55x is accumulator architecture
48
What is the difference between ARM and C55x language?
C55x is an algebraic assembly language
49
What are some key parts of C55x assembly language?
there are intrinsic functions like int_sadd which performs saturating addition
50
What kind of data types does C55x have?
word (16 bits) and longword (32 bits)
51
True or false: C55x instructions never operate on register bits?
false, some instructions do
52
Fill in the blank: Most registers in C55x are _________.
memory-mapped
53
How can you refer to registers in the C55x assembly language?
mnemonic name, memory address
54
What are some extra counters that the C55x architecture has?
in addition to the PC there is also the XPC (program counter extension(allows for multiple pages to run code at once)) and RETA (subroutine return address)
55
What are some other special features of C55x architecture?
there's 4 40-bit accumulators, and multiple status registers
56
What is the SP?
keeps track of user stack pointer
57
What is the SSP?
keeps track of the system stack pointer
58
What is SPH?
extended data page pointer for both SP and SSP
59
What is a prominent auxiliary register in C55x?
CDP for coefficients for polynomial evaluation instructions
60
Which registers are used for circular buffer operations?
BK47, AR4-7
61
What are block repeat registers useful for?
for looping and repeating certain blocks of code
62
What are the 3 addressing modes of C55x?
absolute addressing, direct addressing, indirect addressing
63
What is absolute addressing?
supplying an address in the instruction
64
What is direct addressing?
using an offset
65
What is indirect addressing?
using a register as a pointer
66
What are 2 stacks of C55x?
data and system
67
How many different stack configurations does C55x have?
3
68
Which stack configuration has independent data and system stacks?
Dual 16-bit stack
69
What is the difference between fast and slow return for the dual 16-bit stacks
slow return does not use RETA and CFCT while fast does
70
Which stack configuration modifies SP and SSP by the same amount?
32-bit stack with slow return
71
What are some tips for efficient loops?
no function calls, small loop body, use unsigned int for loop counter, use <= to test LC, make use of compiler (global optimization, software pipelining)

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