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Embedded Software > CPU > Flashcards

CPU Flashcards

1
Q

What is the UART?

A

universal asynchronous receiver transmitter, it provides serial communication

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2
Q

What is a the typical type of interface from I/O device to CPU?

A

digital

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3
Q

How many functions are integrated into the standard PC interface chip?

A

8251

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4
Q

What are serial communication parameters?

A

baud rate, number of bits per character, parity/no parity, even/odd parity, length of stop bit

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5
Q

What types of instructions can support I/O?

A

special purpose I/O instructions and memory-mapped load/store instructions

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6
Q

Which chip provides in, out instructions?

A

Intel x86

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7
Q

What kind of instructions do most CPUs use?

A

memory-mapped

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8
Q

Do I/O instructions preclude memory-mapped I/O?

A

no

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9
Q

Why is busy/wait very inefficient?

A

the CPU can’t do other work while testing the device and it’s hard to do simultaneous I/O

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10
Q

How do you efficiently check the status of I/O device?

A

interrupts

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11
Q

What does the interrupt do?

A

allows a device to change the flow control in the CPU and causes a subroutine call to the handle device

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12
Q

What does the interrupt force?

A

a subroutine call as the next instruction

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13
Q

When interrupt is triggered, how does the CPU know where to go back after the ‘subroutine call’?

A

the return address is saved that way it can go back to the foreground program once the subroutine call is done

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14
Q

How are the CPU and the device connected?

A

through a CPU bus

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15
Q

What is the CPU and device handshake?

A

device asserts interrupt request and CPU asserts interrupt acknowledge when it can handle interrupt

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16
Q

What is a priority?

A

determines which interrupt runs first

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17
Q

What is a vector?

A

determines what code is called for each type of interrupt (table of pointers to the interrupt handlers)

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18
Q

What is masking?

A

when an interrupt with lower priority than the current one is not recognized until the current interrupt is complete

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19
Q

What is the interrupt with highest priority that can never be masked called?

A

non-maskable priority

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20
Q

What is a non-maskable priority often used for?

A

power-down

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21
Q

What is the interrupt sequence?

A

CPU acknowledges a request, device sends vector, CPU calls handler, software processes request, CPU restores state to foreground program

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22
Q

What are some sources of interrupt overhead

A

handler execution time, interrupt mechanism overhead, register save/restore, pipeline-related penalties, cache-related penalties

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23
Q

What 2 types of interrupt does ARM7 support?

A

fast interrupt requests (FIQs), and interrupt requests (IQs)

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24
Q

What location does the interrupt table start at?

A

0

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25
Q

What are the CPU actions of the ARM interrupt procedure?

A

save PC, copy CPSR to SPSR, force bits in CPSR to record interrupt, force PC to vector

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26
Q

What are the handler responsibilities of the ARM interrupt procedure?

A

restore proper PC, restore CSPR from SPSR, clear interrupt disable flags

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27
Q

What is the worst case latency to respond to interrupt with ARM?

A

27 cycles

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28
Q

What is the breakdown for the latency in ARM interrupt?

A

2 cycles for external request synchronization, up to 20 for current instruction, 3 for data abort, and 2 to enter interrupt handling state

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29
Q

What it the latency period for C55x interrupt?

A

between 7 and 13 cycles

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30
Q

What are the two styles of interrupt return for C55x?

A

fast and slow

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31
Q

What are the external interrupts for the ATmega2560?

A

2, 3, 18, 19, 20, 21

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32
Q

What additional bit does the ATmega2560 have in the status register?

A

global interrupt enable bit

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33
Q

What is the interrupt vector’s relationship to priority in the ATmega2560?

A

lower vector = higher priority

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34
Q

What is one of the reasons for supervisor mode?

A

You may want to have a protective barrier between programs

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35
Q

What can supervisor mode prevent?

A

Memory corruption

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36
Q

Does C55x have a supervisor mode?

A

No

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37
Q

What does supervisor mode manage?

A

Various programs

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38
Q

What instruction do you use to enter supervisor mode?

A

SWI

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39
Q

What is SWI similar to?

A

Subroutine

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40
Q

What does the SWI instruction do?

A

sets the PC to 0x08, passed argument to supervisor mode code, and saves the CPSR in the SPSR

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41
Q

What is an exception?

A

an internally detected error

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42
Q

Fill in the blanks: Exceptions are ______ with instructions but _______.

A

synchronous, unpredictable

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43
Q

True or false: Exceptions are usually prioritized but not vectorized?

A

false, they are usually both prioritized AND vectorized

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44
Q

What is a trap?

A

a software interrupt that is an exception generated by an instruction

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45
Q

What does a trap do?

A

calls supervisor mode

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46
Q

What is a co-processor?

A

an added function unit that is called by instruction

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47
Q

How many designer-selected co-processors does ARM allow?

A

up to 16

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48
Q

Does C55x use co-processors as well?

A

yes

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49
Q

What are often structured as co-processors?

A

floating-point units

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50
Q

What are some available C55x image/video hardware extensions?

A

DCT(discrete cosine transform)/IDCT, pixel interpolation, and motion estimation

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51
Q

Which C55x devices have image/video hardware extensions?

A

5509 and 5510

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52
Q

True or false: Only one memory location is mapped onto one cache entry?

A

false, many are

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53
Q

What can you have caches for?

A

instructions, data, or unified data and instructions

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54
Q

With caches, is memory access time deterministic?

A

no

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55
Q

What is a cache hit?

A

when a required location is in a cache

56
Q

What is a cache miss?

A

when a required location is not in cache

57
Q

What is a working set?

A

set of locations used by program in a time interval

58
Q

What are some types of misses?

A

compulsory (cold), capacity, and conflict

59
Q

What is a compulsory (cold) miss?

A

location has never been accessed

60
Q

What is a capacity miss?

A

working set is too large

61
Q

What is a conflict miss?

A

multiple locations in a working set map to same cache entry

62
Q

What is the formula for average memory access time?

A

-tav = htcache + (1-h)tmain
(h=cache hit rate, tcache = cache access time, tmain = main memory access time)

63
Q

What is the formula for average memory access time for a multilevel cache?

A

-tav = h1tl1 + h2tl2 + (1-h2-h1)*tmain

64
Q

What is a replacement policy?

A

a strategy for choosing which cache entry to throw out to make room for a new memory location

65
Q

What are two popular replacement strategies?

A

random and least-recently used (LRU)

66
Q

What are some different cache organizations?

A

fully-associative, direct-mapped, and n-way set-associative

67
Q

What is a fully-associative cache organization?

A

any memory location can be stored anywhere in the cache (almost never implemented)

68
Q

What is a direct-mapped cache organization?

A

each memory location maps onto exactly one cache entry

69
Q

What is an N-way set-associative cache organization?

A

each memory location can go into one of n sets

70
Q

What are some performance benefits of caches?

A

keeps frequently-accessed locations in fast cache, cache retrieves more than one word at a time, sequential accesses are faster after first access

71
Q

What are some different types of write operations?

A

write-through and write-back

72
Q

What is a write-through operation?

A

immediately copy write to main memory (highly consistent)

73
Q

What is a write-back operation?

A

write to main memory only when location is removed from cache

73
Q

With direct-mapped caches, are conflict misses easy to generate?

A

yes

73
Q

With direct-mapped caches, is only one location mapped to a cache block?

A

no, many are

73
Q

What are some example caches from StrongARM?

A

16KByte, 32-way, 32-byte block instruction, 16 KByte, 32-way, 32-byte block data

73
Q

What kinds of caches do C55x have??

A

various models have 16KB, 24KB cache

74
Q

What does memory management allow?

A

programs to move in physical memory during execution and virtual memory

75
Q

What is virtual memory?

A

memory images kept in secondary storage that are returned to main memory on demand during execution

76
Q

What is a page fault?

A

request for location not resident in memory

77
Q

What does address translation require?

A

some sort of register/table to allow arbitrary mappings of logical to physical addresses

78
Q

What are two basic address schemes

A

segmented and paged

79
Q

Can segmentation and paging be combined?

A

yes

80
Q

What do large translation tables require?

A

main memory access

81
Q

What is a TLB?

A

a cache for address translation

82
Q

Is a TLB typically big or small?

A

small

83
Q

What are the memory region types in ARM?

A

section (1Mbyte), large page (64kbytes), and small page (4kbytes)

84
Q

What is an address in ARM marked as?

A

either section-mapped or page-mapped

85
Q

ARM has a how many level translation scheme?

A

2

86
Q

What are the elements of CPU performance?

A

cycle time, CPU pipeline, and memory system

87
Q

What is pipelining?

A

several instructions are executed simultaneously at different stages of completion

88
Q

What can cause pipeline bubbles?

A

branches, memory system delays, etc.

89
Q

What do pipeline bubbles do?

A

reduce utilization

90
Q

What are some performance measures?

A

latency and throughput

91
Q

What is latency?

A

the time it takes for an instruction to get through the pipeline

92
Q

What is throughput?

A

number of instructions per time period

93
Q

How does pipelining affect latency and throughput?

A

increases throughput without reducing latency

94
Q

ARM 7 has a how many stage pipe?

A

3

95
Q

What are the stages of the ARM 7 pipeline?

A

fetch instructions from memory, decode opcode and operands, execute

96
Q

What is a pipeline stall?

A

when every step cannot be completed in the same amount of time

97
Q

How do bubbles introduced by stall affect latency and throughput?

A

increase latency and reduce throughput

98
Q

What often introduce stalls?

A

branches (branch penalty)

99
Q

What may stall time depend on?

A

whether branch is taken or not

100
Q

What might need to happen during a branching operation with pipelining?

A

squash instructions that already started executing

101
Q

When does the CPU know what to fetch?

A

once the condition is evaluated

102
Q

What can increase pipeline efficiency?

A

a delayed branch mechanism

103
Q

What is a delayed branch mechanism?

A

requires n instructions to be executed after branch whether branch is executed or not

104
Q

How to calculate t loop?

A

tinit + N(tbody + tupdate) + (N-1)ttest,worse + ttest,best

105
Q

C55x has a how many stage pipeline?

A

7

106
Q

What are the stages of the C55x pipe?

A

fetch, decode, address, access1, access2, read stage, execute

107
Q

What does the address stage of the C55x pipe do?

A

computes data/branch addresses

108
Q

What does the access1 stage of the C55x pipe do?

A

reads data

109
Q

What does the access2 stage of the C55x pipe do?

A

finishes data read

110
Q

What does the read stage of the C55x pipe do?

A

puts operands on internal busses

111
Q

Why does C55x handle pipelining better?

A

because of the block registers pipelines won’t break with loop or branch cases

112
Q

What is a cache miss penalty?

A

added time due to a cache miss

113
Q

With what are modern CPU’s designed to keep in mind?

A

power consumption

114
Q

What does heat depend on?

A

power consumption

115
Q

What does battery life depend on?

A

energy consumption

116
Q

What are some causes of CMOS power consumption?

A

Voltage drops, toggling, and leakage

117
Q

What is power consumption proportional to?

A

V^2

118
Q

In regards to toggling what means more power?

A

more activity

119
Q

How can leakage be eliminated?

A

by disconnecting power

120
Q

What is a power saving strategy related to voltage drop?

A

reducing power supply voltage

121
Q

What are some power saving strategies related to toggling?

A

run at a lower clock frequency and disable function units with control signals when not in use

122
Q

What is a power saving strategy related to leaking?

A

disconnect parts from power supply when not in use

123
Q

What are some power management styles?

A

static power management, and dynamic power management

124
Q

Which power management strategy depends on CPU activity?

A

dynamic power management

125
Q

What are some ways the PowerPC 603 use dynamic power management?

A

uses static logic, can shut down unused execution units, and cache is organized into subarrays to minimize amount of active circuitry

126
Q

What is an example of static power management?

A

user-activated power-down mode

127
Q

What are the costs associated with going into a power-down mode?

A

time and energy

128
Q

What does the CPU determine regarding power-down mode?

A

if it is worthwhile going into that mode

129
Q

How can we model CPU power states?

A

with a power state machine

130
Q

What are some power-saving strategies the StrongARM SA-1100 uses?

A

processor takes 2 supplies (3.3v or 1.5v) and there are 3 power modes

131
Q

What are the 3 power modes of the StrongARM SA-1100?

A

run, idle, and sleep

132
Q

What does the idle power mode of the StrongARM SA-1100 do?

A

stops CPU clock with logic still powered

133
Q

What does the sleep power mode of the StrongARM SA-1100 do?

A

shuts off most chip activity: 3 steps, each about 30 microseconds, wakeup takes >10ms

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