Qs I got wrong Flashcards
Explain how a logic component which takes in n inputs and outputs m outputs can be seperated into similar components
Combinatorial lofic component comtinuously computes the outputs from inputs alone
for a component
f: B^n -> B^m we can define
fi: B^n -> B
therefore
f(x) = f0(x) || f1(x) || … || fm-1(x)
What are the two key things an FSM machine will do during a clock cycle
compute r = w(Q,x)
an output
and
Q’ = g(Q,x)
a next state
Why must an FSM’s clock cycle be limited by the critical path
Because if the clock cycle ends before the output pr the next state is calculated the fsm will malfunction
why does the program counter not have to be addressable as a general purpose register
the program counter does have a special purpose but that can be realised by addressing it as a GPR
but it does not have to be done that way as it has specific instructions
Why is it harder to alter the ISA than the associated micro architecture
the ISA is exposed to the software unlike the micro arch
so altering ISA potentially impiles altering software along with compiler os etc
while micro arch doesn’t
when will a hardware interrupt be handled
Hardware interrupts are asynchronous with the fde cycle so can occur at any time and the processor will check for interrupts at the start of the fetch and so the hardware interrupt will be handled then
define a buffer overflow
data is written beyond the bounds of the buffer allowed for memoyr
why is an address base and size for a program not enough to stop all cases of buffer overflow
is the address is beyond the bounds of the array but within the buffer allocated.
in ARM v7 A what is the pc also known as
r15
in ARM V7 A what is j
an unconditional branch
When checking how many bits are needed to store an instruction what are the key things to remember
the off set of an address if applicable
if its byte addressable only find out the capacity in bytes not bits
Explain how CPU read from memory in synchronuous busses
CPU sends memory address
signals read request
waits fied amount of clock cycles
CPU copies data off bus
CPU removes read request signals
Explain how CPU read from memory in asynchronuous busses
CPU send memory address
signals read request
CPU signals ready
waits until memory signals read
CPU copies of bus
CPU removes read request
