Each state needs a unique codeword.
Name the three main types of code we use
Direct State-Output map
Discuss the effect of code density when encoding the states
Density affects number of flip-flops in circuit: one flip-flop per codeword bit
In some state-code styles, density can be made high or low, according to design choice in code construction details
Dense codes generally lead to combinational logic with high fan-in (many inputs combined to each output). This may lead to poor FPGA logic cell utilisation, but may give efficient combinational gate area use in ASIC
Flip-flops tend to be plentiful on FPGA: reducing code density (increasing sparsity) does not necessarily increase FPGA fabric cost
Sparse (low-density) codes may result in simple combinatorial functions, leading to low delay (high speed) in both FPGA and ASIC
Sparse codes may give simple interconnect structure, simplifying interconnect (wire) routing problem (especially important on FPGA)
Dense codes may ease clock energy consumption in circuits with a very high number of states (fewer flip-flops to be driven by clock signal)
Describe the use of unit-distance codes for state encoding.
Mention any difficulties and possible solutions
Unit-distance codes aim for each new state to differ by at most one bit to the previous state.
Can be designed dense (Gray) or sparse (Thermometer)
Gray code, Johnson code, Thermometer code
Sometimes it is impossible to do this for every transition
We can solve this by adding duplicate states or adding link states
Describe the one-hot state encoding style
One bit per state, each codeword has one bit true ("hot") and all others false.
This creates a sparse code.
Many invalid codewords but very easy to identify them
Describe the Direct state-output map method for encoding states
Each output codeword is a field within each encoded state, so no additional logic is required for generation of the output signals
We start with a list of the outputs for each state. If they are not unique we add an additional bit to differentiate them (with *s as necessary) until theya re all unique.
Describe the 0.7 RC model for a CMOS gate
Describe the 0.7RC model for interconnect
What is clock skew ?
It is the difference in the arrival time of the same clock edge at individual flip-flops.
t5 -t1 in this diagram
Why do we need to consider the initialisation of an FSM?
What are some solutions?
On power on we need to ensure that the FSM begins in the correct state and not any invalid codewords or just the wrong point in a sequence.
We can provide special circuitry to initialise the FSM (set/reset/clear)
We can ensure that the FSM operates correctly, regardless of starting state.
Describe a Lock-out state in an FSM
Typically by accident, these are unused states which have no transition path back to the intended design.