Unit 5 Flashcards
An operational element, such as an AND gate or an ALU
combinational element
A memory element, such as a register or a memory
state element
The approach used to determine when data is valid and stable relative to the clock
clocking methodology
A clocking scheme in which all state changes occur on a clock edge
edge-triggered clocking
A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit
control signal
A unit used to operate on or hold data within a processor
datapath element
The register containing the address of the instruction in the program being executed
program counter (PC)
A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed
register file
To increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item
sign extend
A branch where the branch condition is satisfied and the program counter (PC) becomes the branch target
branch taken
A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch
branch not taken
An implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical
single clock cycle implementation
implementation technique in which multiple instructions are overlapped in execution, much like an assembly line
pipelining
When a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute
structural hazard
When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available
pipeline data hazard (or data hazard)
A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory
forwarding or bypassing
A specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction
load use data hazard
A stall initiated in order to resolve a hazard
pipeline stall or bubble
When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected
control or branch hazard
A method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome
branch prediction
The number of stages in a pipeline or the number of stages between two instructions during execution
pipeline latency
An instruction that does no operation to change state
nop
An interrupt for which the address to which control is transferred is determined by the cause of the exception.
vectored interrupt
