Unit 6 Flashcards

1
Q

The locality principle stating that if a data location is referenced, data locations with nearby addresses will tend to be referenced soon

A

spatial locality

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2
Q

The locality principle stating that if a data location is referenced then it will tend to be referenced again soon.

A

temporal locality

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3
Q

A structure that uses multiple levels of memories; as the distance from the processor increases, the size of the memories and the access time both increase.

A

memory hierarchy

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4
Q

The minimum unit of information that can be either present or not present in a cache.

A

block/line

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5
Q

The fraction of memory accesses found in a level of the memory hierarchy

A

hit rate

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6
Q

The fraction of memory accesses not found in a level of the memory hierarchy

A

miss rate

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7
Q

The time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or a miss

A

hit time

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8
Q

The time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor

A

miss penalty

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9
Q

One of the segments that make up a track on a magnetic disk; a sector is the smallest amount of information that is read or written on a disk

A

sector

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10
Q

A cache structure in which each memory location is mapped to exactly one location in the cache

A

direct mapped cache

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11
Q

A field in a table used for a memory hierarchy that contains the address information required to identify whether the associated block in the hierarchy corresponds to a requested word

A

tag (cache)

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12
Q

A field in the tables of a memory hierarchy that indicates that the associated block in the hierarchy contains valid data

A

valid bit

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13
Q

A request for data from the cache that cannot be filled because the data are not present in the cache

A

cache miss

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14
Q

A scheme in which writes always update both the cache and the next lower level of the memory hierarchy, ensuring that data are always consistent between the two

A

write through

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15
Q

A queue that holds data while the data are waiting to be written to memory

A

write buffer

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16
Q

A scheme that handles writes by updating values only to the block in the cache, then writing the modified block to the lower level of the hierarchy when the block is replaced

A

write back

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17
Q

A scheme in which a level of the memory hierarchy is composed of two independent caches that operate in parallel with each other, with one handling instructions and one handling data

A

split cache

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18
Q

A cache structure in which a block can be placed in any location in the cache

A

fully associative cache

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19
Q

A replacement scheme in which the block replaced is the one that has been unused for the longest time

A

least recently used (LRU)

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20
Q

A memory hierarchy with multiple levels of caches, rather than just a cache and main memory

A

multilevel cache

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21
Q

The fraction of references that miss in all levels of a mutlilevel cache

A

global miss rate

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22
Q

The fraction of references to one level of a cache that miss; used in multilevel hierarchies

A

local miss rate

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23
Q

how long a component is expected to last

A

mean time to failure (MMTF)

24
Q

percentage of devices expected to fail in a given year

A

annual failure rate (AFR)

25
MTTR
mean time to repair
26
sum of MTTF + MTTR
mean time between failures (MTBF)
27
A code that enables the detection of an error in data, but not the precise location and, hence, correction of the error
error detection code
28
emulation methods that provide standard software interface
virtual machine
29
software that supports VMs
virtual machine monitor (VMM) or hypervisor
30
A technique that uses main memory as a "cache" for secondary storage
virtual memory
31
An address in main memory
physical address
32
A set of mechanisms for ensuring that multiple processes sharing the processor, memory, or I/O devices cannot interfere, intentionally or unintentionally, with one another by reading or writing each other's data. These mechanisms also isolate the operating system from a user process
protection
33
An event that occurs when an accessed page is not present in main memory
page fault
34
An address that corresponds to a location in virtual space and is translated by address mapping to a physical address when memory is accessed
virtual address
35
The process by which a virtual address is mapped to an address used to access memory
address translation or mapping
36
A variable-size address mapping scheme in which an address consists of two parts: a segment number, which is mapped to a physical address, and a segment offset
segmentation
37
The table containing the virtual to physical address translations in a virtual memory system. The table, which is stored in memory, is typically indexed by the virtual page number; each entry in the table contains the physical page number for that virtual page if the page is currently in memory
page table
38
The space on the disk reserved for the full virtual memory space of a process
swap space
39
A field that is set whenever a page is accessed and that is used to implement LRU or other replacement schemes
reference bit (or use or access bit)
40
A cache that keeps track of recently used address mappings to try to avoid an access to the page table
translation lookaside buffer (TLB)
41
A cache that is accessed with a virtual address rather than a physical address
virtually addressed cache
42
A cache that is addressed by a physical address
physically addressed cache
43
A situation in which two addresses access the same object; it can occur in virtual memory when there are two virtual addresses for the same physical page
aliasing
44
A mode indicating that a running process is an operating system process
supervisor/kernel mode
45
A special instruction that transfers control from user mode to a dedicated location in supervisor code space, invoking the exception mechanism in the process
system call
46
A changing of the internal state of the processor to allow a different process to use the processor that includes saving the state needed to return to the currently executing process
context switch
47
A signal or action that controls whether the process responds to an exception or not; necessary for preventing the occurrence of exceptions during intervals before the processor has safely saved the state needed to restart
exception enable
48
An organization of disks that uses an array of small and inexpensive disks so as to increase both performance and reliability
redundant arrays of inexpensive disks (RAID)
49
allocation of logically sequential blocks to separate disks to allow higher performance than a single disk can deliver
RAID 0 striping (no redundancy)
50
writing identical data to multiple disks
RAID 1 mirroring
51
error detection and correction
RAID 2
52
bit interleaved parity (protection groups that share a common check disk)
RAID 3
53
block interleaved parity
RAID 4
54
distributed block interleaved parity
RAID 5
55
P + Q redundancy
RAID 6
56