Unit 7 Flashcards
(27 cards)
von Neumann model
programs and data are stored together in the same memory input output and storage connected via processing unit
stored program concept
program instructions must be held in main memory to be executed, machine code instructions fetched from main memory, executed serially by a processor, that performs arithmetic and logical operations
harvard architecture
physically seperate memories for data and instructions, potentially faster, address and word length can be different but memory can be inefficient
the processor
processes the fetch execute cycle
control unit
coordinates and controls the operations carried out by the computer, decides what instructions, deciphers instruction
arithmetic/logic unit (ALU)
performs mathematical and logical operations
registers
specialized very high speed small memory units directly accessed by the CPU
system bus
control bus, address bus, data bus
control bus
control signals directing the components
-signal can travel both ways
- transmit command, timing and status signals between components f ex interrupt request, clock signals, reset
address bus
when the CPU wants to access a particular memory location
-signal travels one way
-Usually 8, 16, 32 or 64 separate lines wide
-Memory is split up into units called words
the width of the address bus is a key factor in determining the maximum possible capacity of the Main Memory
data bus
data returned back from memory
-signals can travel both ways
-Usually 8, 16, 32 or 64 separate lines wide
-Used for moving data & instructions between components
-Data bus width is a key factor affecting overall system performance.
general purpose register
accumulators, it is in the ALU.
Main memory unit
everything that processor is going to use is stored there (all of the program instructions and data needed)
-parts of operating system which the computer is using
Memory registers
-program counter (keeps track of where to find the next instruction)
-current instruction register
-memory address register
-memory buffer/data register
status register
stores information about result of last instruction that ALU executed
-flag to indicate error
registers of the CPU
program counter, current instruction register, memory address register, memory buffer register, accumulator which holds results
fetch
-The PC (Program Counter) holds the address of the next instruction. This address is copied to the MAR using the address bus
-Contents of the address location identified by the MAR are copied into the MBR using the data bus
-PC is incremented by 1
-Contents of the MBR are copied to the CIR
decode
-Contents of the CIR are divided into its individual parts, the opcode and operand
-The address part goes to the MAR and the data within it is fetched and goes to the MBR
-The control unit then interprets (decodes) the operation code so the processor knows what to do
opcode
the binary code for the operation to be carried out
operand
the address/value of the data/instruction that will be used by the operation
execute
-address sent to MBR to be executed
-control unit sends signal telling main memory it has to be read
register and buses used in fetch
register: PC, MAR, MBR, CIR buses:all
register and buses used in decode
register: CIR buses:none
register and buses used in execute
registers: CIR MAR ACC buses: address
