Program Operation Flashcards

(83 cards)

1
Q

What is the main topic of Lecture 9?

A

How a microcontroller program runs internally: CPU architecture components and the fetch–decode–execute cycle, illustrated with a C program translated to assembly on the ATmega328.

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2
Q

Which core CPU registers were introduced earlier in the module and recapped here?

A

General purpose registers, status register, program counter, and stack pointer.

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3
Q

Which of those registers can the programmer directly access and manipulate?

A

General purpose registers, status register, and stack pointer (the program counter is mostly handled by hardware, but can be affected indirectly by jumps/calls).

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4
Q

What is the ALU (Arithmetic Logic Unit)?

A

The part of the processor that performs arithmetic and logical operations on data from storage.

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5
Q

What width is the ALU in the ATmega328?

A

8-bit.

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6
Q

What are the ALU’s inputs and outputs?

A

Two 8-bit inputs, an opcode (operation), an 8-bit result, and status flags (e.g. carry, zero) written to the status register.

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7
Q

Where are the ALU’s status flags stored?

A

In the status register (SREG).

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8
Q

In general, how does the ALU operate on data?

A

Data are loaded from storage into the ALU inputs, an arithmetic/logic operation (ADD, SUB, AND, OR, etc.) is performed, and the result is written back to storage.

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9
Q

What is an example AVR instruction handled by the ALU?

A

ADD (add without carry) – it adds two registers and updates flags.

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10
Q

What are the four main highlighted components in the ATmega328 CPU core diagram?

A

General purpose registers, program counter, stack pointer, and status/control register, plus the ALU.

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11
Q

How many general purpose registers does the ATmega328 have and how wide are they?

A

32 registers, each 8 bits wide.

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12
Q

What is the width of the program counter (PC) in the ATmega328?

A

14 bits.

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13
Q

What does the program counter store?

A

The address of the next instruction or operand to be fetched.

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14
Q

What is the stack pointer used for?

A

It holds the address of the top (last item) of the stack in SRAM.

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15
Q

What is the stack used for in a microcontroller?

A

Temporarily storing data, return addresses, and MCU state via push/pop during function calls and interrupts.

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16
Q

What does the status and control register (SREG) hold?

A

Flags describing the state of the processor after the last instruction (e.g. Zero, Carry) and some control bits (e.g. global interrupt enable).

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17
Q

Where are the general purpose registers located in the memory space?

A

At the bottom of the data space so they can be accessed directly by the ALU.

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18
Q

What is an accumulator in lower-spec CPUs?

A

A single register used for most arithmetic and logic operations instead of a register file.

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19
Q

Which simplified block diagram is used in this lecture?

A

A microcontroller core showing CPU, clock, control unit, MAR, MDR, IR, instruction decoder, and buses.

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20
Q

What does the clock do in a microcontroller?

A

Generates a periodic high/low signal that synchronises the actions of all internal components.

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21
Q

What waveform does a typical microcontroller clock generate?

A

A square wave with (ideally) 50% duty cycle and fixed frequency.

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22
Q

What is meant by “duty cycle”?

A

The fraction of one clock period during which the signal is high (e.g. 50% means high for half, low for half).

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23
Q

What happens at each clock cycle with respect to instruction execution?

A

One step in the fetch–decode–execute cycle is performed.

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24
Q

What internal clock does the ATmega328 ship with?

A

An internal RC oscillator at 8 MHz.

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25
What external clock does the Arduino Nano board typically use?
A 16 MHz crystal.
26
Why is the internal RC oscillator less accurate than a crystal?
Manufacturing variations cause frequency errors (often a few %), although it can be calibrated.
27
What are two advantages of using the internal RC oscillator?
It is cheaper and frees up the external clock pins for other uses, simplifying PCB design.
28
Why might an external crystal/resonator still be needed?
For applications requiring accurate timing and frequencies, e.g. communication protocols like CAN, USB, Ethernet.
29
What is the main purpose of the clock distribution network inside the ATmega328?
To distribute the clock signal to all major subsystems so they operate in lock-step and stay synchronised.
30
What are the CKSEL3..0 bits?
Fuse bits in flash that select the clock source and options for the ATmega328.
31
What two clock-related registers are accessible to the programmer?
OSCCAL (Oscillation Calibration Register) and CLKPR (Clock Prescale Register).
32
What is OSCCAL used for?
Trimming/calibrating the internal RC oscillator to compensate for process variation.
33
What is CLKPR used for?
Setting the prescaler division factor between the main clock and the CPU system clock to change speed at run-time.
34
What does the control unit do?
Coordinates and controls CPU activities, sending control signals to ALU, memory, and I/O based on decoded instructions.
35
Name four responsibilities of the control unit.
Coordinate CPU activities, Manage data flow between components, Accept the next instruction, Store results back to memory.
36
What is the Memory Address Register (MAR)?
A register which holds the address of memory being accessed (read/write).
37
Where does the MAR get its value from during instruction fetch?
From the program counter (PC).
38
What is the Memory Data Register (MDR)?
A register that temporarily holds data read from or written to memory.
39
What is the Instruction Register (IR)?
A register where the current instruction opcode is stored after being fetched from memory.
40
What is the Instruction Decoder (ID)?
Logic that decodes the instruction in the IR, identifies which operation it is, and generates control signals to execute it.
41
What does the instruction decoder contain internally?
A lookup table/mapping of all binary opcodes in the instruction set architecture.
42
What are buses in a microcontroller?
Parallel connections used by components to communicate: address, data, and control buses.
43
What does the address bus do?
Carries memory or I/O addresses from the CPU to memory/controllers; it is unidirectional.
44
What does the data bus do?
Carries data and instructions between CPU and memory; it is bidirectional.
45
How wide is the AVR CPU data bus?
8 bits.
46
What is the word size on AVR and why does that matter?
16 bits; fetching a 16-bit word requires two 8-bit transfers, often taking two cycles.
47
What does the control bus do?
Carries command, timing, and status signals (e.g. read/write, bus request/grant, clock sync, reset).
48
What does a program instruction consist of?
An opcode (operation to perform) and operand(s) (data or addresses).
49
Give a high-level C example used in the lecture.
myVariable = 121 + 103;
50
Give the equivalent low-level assembly sequence for that example.
LDI r16, 0b01111001 LDI r17, 0b01100111 ADD r16, r17 STS 0xFF00, r16.
51
How is this instruction sequence represented in machine code?
As a sequence of binary patterns like 1110011100001001, etc. (each 16- or 32-bit instruction).
52
What is the fetch–decode–execute cycle?
The repeating sequence of steps the CPU uses to run each instruction in a program.
53
What are the three main stages of the FDE cycle?
Fetch, Decode, Execute (then repeat).
54
What happens during the fetch stage?
The next instruction is fetched from memory: PC address goes to MAR, memory is read, data goes via MDR to IR, and PC is incremented.
55
How does the CPU know which address to fetch from?
It uses the value stored in the program counter (PC).
56
What happens to the PC during fetch?
It is incremented to point to the next sequential instruction (unless later modified by a branch/call).
57
What happens during the decode stage?
The instruction in IR is decoded by the instruction decoder; it determines the operation type and any extra data required.
58
What might happen during decode if more data is needed?
Additional bytes are fetched from memory using the address and data buses (for immediates, addresses, etc.).
59
What happens during the execute stage?
The CPU performs the requested operation: ALU calculations, memory reads/writes, register updates, or control flow changes.
60
What happens after execute?
The cycle repeats: the next instruction address in PC is used to begin the next fetch–decode–execute sequence.
61
In the algorithm description, what is Step 1?
MAR <- (PC) – copy the program counter value into the memory address register.
62
In the algorithm description, what is Step 2?
(PC) <- (PC) + 1 – increment the program counter.
63
In the algorithm description, what is Step 3?
MDR <- (MAR) – load from memory at address MAR into the memory data register.
64
In the algorithm description, what is Step 4?
IR <- (MDR) – load the MDR contents into the instruction register for decoding.
65
Which C program is revisited in this lecture?
The digital I/O program with two buttons on D2/D3 controlling two LEDs on D8/D9.
66
What does this program configure DDRD bits 2 and 3 as?
Inputs (for the push buttons).
67
What does the program configure DDRB bits 0 and 1 as?
Outputs (for the LEDs).
68
Why is PORTD OR-ed with 0b00001100 in the C code?
To enable internal pull-up resistors on Port D bits 2 and 3.
69
What does the infinite for(;;) loop do?
Continuously checks button states and updates LEDs accordingly.
70
What file does the assembler generate that shows C to assembly translation and addresses?
A listing file.
71
What information is shown in the listing file?
Memory addresses, generated assembly instructions, and the original C lines they came from.
72
In the listing, what is the first IN instruction for main?
8a b1 or in assembly: in r24, 0x0a.
73
What is the binary form of this instruction?
1011 0001 1000 1010.
74
Which part of the binary identifies the opcode?
The most significant 5 bits 10110, which correspond to IN.
75
How are the remaining bits divided according to the opcode format?
Opcode 10110, then AA, ddddd (destination register), and AAAA (I/O address bits).
76
What destination register and I/O address does in r24, 0x0a use?
Destination register r24 and I/O register address 0x0A (DDRD).
77
In words, what does in r24, 0x0a do?
Reads the contents of I/O register 0x0A (DDRD) into register r24.
78
During execute, which address is placed into MAR for the IN instruction?
The I/O register address 0x0A (DDRD).
79
What happens after MAR is set to 0x0A?
The memory controller reads the contents of that I/O register onto the data bus into the MDR.
80
Where does the MDR value go next in the example?
Into general purpose register R24.
81
What table is given at the end of the lecture?
A table mapping assembly instructions (e.g. LDI, ADD, STS) to their machine code bit patterns and manual references.
82
What does the machine code for ldi r16, 0b01111001 look like?
Pattern like 1110 0111 0000 1001 (an example 16-bit AVR encoding).
83
What does the machine code for sts 0xFF00, r16 require?
A 32-bit instruction: opcode plus 16-bit address (two words).