Describe and illustrate adder using D Flip Flop
One register can be used for storing both the augend and sum bits by shifting the sum into A while the bits of A are shifted out.
The carry out of the full adder is transferred to a D
flip-flop.
The output of the D flip-flop is then used as carry
input for the next pair of significant bits.
*See page 25
Describe and illustrate an adder using JK Flip Flop
The serial outputs from registers are designated by x and y.
The sequential circuit proper has two inputs, x and y, that provide a pair of significant bits, an output S that generates the sum bit, and flip-flop Q for storing the carry.
*See page 26
Do the example question (0100+0111)
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Describe the universal shift register
Shift registers are often used to interface digital system situated remotely from each other.
If the distance is far, it will be expensive to use n lines to transmit the n bits in parallel.
Transmitter performs a parallel-to-serial conversion of data and the receiver does a serial-to-parallel conversion.
If the register has both shifts and parallel load capabilities, it is referred to as a universal shift register.
Describe the various shift register capabilities
A clear control to clear the register to 0.
A clock input to synchronize the operations.
A shift-right control to enable the shift operation and the serial input and output lines associated with the shift right.
A shift-left control to enable the shift operation and the serial input and output lines associated with the shift left.
A parallel-load control to enable a parallel transfer and the n input lines associated with the parallel transfer.
n parallel output lines.
A control state that leaves the information in the register unchanged in the presence of the clock.
If the register has both shifts and parallel load capabilities, it is referred to as a universal shift register.
Go through the example on universal registers on page 30
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Describe counters
Counters are sequential circuits which “count” through a specific state sequence. They can count up, count down, or count through other fixed sequences.
A counter that follows the binary number sequence is called a binary counter.
What are the different types of counters with illustrations
Ripple Counters (Asynchronous)
Clock connected to the flip-flop clock input on the LSB bit flip-flop
For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous!
Output change is delayed more for each bit toward the MSB.
Synchronous Counters
Clock is directly connected to the flip-flop clock inputs
Logic is used to implement the desired state sequencing
Examples: Up Counters, Down Counters, Up/Down Counters
*See page 33
What are the applications of ripple counter
These counters are frequently used for measurement of Time, Measurement of Frequency, Measurement of Distance, Measurement of Speed, Waveform generation, Frequency Division, Digital Computers, Direct Counting
etc….
Compare the synchronous and asynchronous counter
Also called
SC-Parallel Counter
AC- Serial Counter
Principle of operation:
SC-Each flip flop is triggered with same clock signal at
the same time.
AC- The first flip flop drives the clock signal of the next flip flop
Decoding errors
SC- Not produced
AC-Produced
Operating speed
SC- Fast
AC- Comparatively slow
Delay in signal propagation
SC- Very Low
AC- Comparatively high
Count sequence
SC- Not Fixed
AC- Fixed
Response to clock signal
SC- Each flip-flop changes its state simultaneously.
(clocked Simultaneously)
AC- There is no simultaneous change in the state of all flip flops with change in clock input. (not clocked
simultaneously)
Flip-flop direct interconnection
SC- Not Exist
AC- Exist
How many states can a ripple counter count
A n-bit ripple counter can count up to 2n states.
Explain using characteristic tables why Ripple counter designing is done using T and JK flip flops
For Ripple counter designing the flip flop should contain a condition for toggling of states. This condition is satisfied by only T and JK flip flops.
*See page 36
Explain why D flip flops are not used for ripple counter construction
Ripple counter D flip flop has initial value as 1. When the clock pulse undergoes the transition from 1 to 0 the flip flop should change the state. But according to truth table when D value is 1 it stays on 1 until D value is changed to 0. So, the waveform of D flip flop will always stay 1, which is not useful for counting.
So, D flip flop is not considered for construction of Ripple Counters.
Describe and illustrate how 2-Bit Ripple Counter using JK Flip Flop
JK inputs maintained at a state 1 - supplied with high voltage signal.
Negative triggered clock pulse.
Output Q0 is the LSB and the output Q1is the MSB bit.
Initially, the flip flop is at state 0.
Flip-flop stays in the state until the applied clock goes from 1 to 0.
As the JK values are 1, the flip flop should toggle. So, it changes state from 0 to 1.
The process continues for all pulses of the clock.
The counter counts the values 00,01,10,11 then resets itself and starts again
*See page 37
Describe and illustrate 3-Bit Ripple Counter using
JK Flip Flop
the counter can count up to 2^3 = 8 values .i.e.
000,001,010,011,100,101,110,111.
*See page 38
Describe and illustrate 3-Bit Ripple Counter using
JK Flip Flop
*See page 39
Describe and illustrate the four-bit binary ripple counter
The count starts with binary 0 and increments by
1 with each count pulse input. After the count of 15, the counter goes back to 0 to repeat the count.
The least significant bit, A0, is complemented
with each count pulse input. Every time that A0
goes from 1 to 0, it complements A1.
Every time that A1 goes from 1 to 0, it
complements A2
Every time that A2 goes from 1 to 0, it complements A3, and so on for any other higher order bits of a ripple counter.
*See page 40
Describe and illustrate the BCD(DECADE) Ripple Counter
A decimal counter follows a sequence of ten states and returns to 0 after the count of 9.
This is similar to a binary counter, except that the state after 1001 is 0000.
The operation of the counter can be explained by a list of conditions for flip-flop transitions
*See page 41
Describe synchronous counters
Synchronous counters are different from ripple counters in that clock pulses are applied to the inputs of all flip-flops.
A common clock triggers all flip-flops simultaneously rather than one at a time in succession as in a ripple counter.
Individual output bits change state at exactly the same time in response to the common clock signal with no ripple effect and therefore, no major propagation delay.
Describe the binary counter
Synchronous binary counters have a regular pattern and can be constructed with complementing
flip-flop and gates
*Page 45
Look at page 46 and 47 at the Binary 4-bit
Synchronous Up Counter and the Binary 4-bit
Synchronous Down Counter
*
Describe the Up-Down Binary Counter
The two operations can be combined in one
circuit to form a counter capable of counting up or down.
It has an up control input and down control input.
*See page 48
Describe the process of drawing the circuit of the BCD Counter
Because of the return to 0 after a count of 9, a BCD counter does not have a regular pattern as in a straight binary count.
To derive the circuit of a BCD synchronous counter, it is necessary to go through a sequential circuit design procedure.
The flip flop input equations can be simplified by means of maps. The simplified functions are
TQ1=1
TQ2=Q8’Q1
TQ4=Q2Q1
TQ8=Q8Q1+Q4Q2Q1
y=Q8Q1
The circuit can be easily drawn with four T flip-flops, five AND gates, and one OR gate.
Draw the state table of the BCD Counter
page 50
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INTRODUCTION8
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NUMBER SYSTEMS18
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BOOLEAN ALGEBRA AND LOGIC GATES17
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CANONICAL AND STANDARD FORMS11
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GATE LEVEL MINIMIZATION21
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COMBINATIONAL LOGIC30
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COMBINATIONAL LOGIC II19
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SYNCHRONOUS SEQUENTIAL LOGIC29
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SYNCHRONOUS SEQUENTIAL LOGIC II23
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REGISTERS AND COUNTERS31
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REGISTERS AND COUNTERS II26
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MEMORY AND PROGRAMMABLE LOGIC21
