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(77 cards)

1
Q

What are the three types of unconditional jump instructions?

A

short, near, far, wherever you are

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2
Q

allows a branch to within +127 and -128 bytes

A

Short Jump

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3
Q

allows a jump to any location in the current code segment

A

Near Jump

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4
Q

allows a jump to any location in the memory system

A

Far Jump

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5
Q

Whenever a label appears with a JMP instruction or conditional jump, the label, must be followed by a ______

A

Colon

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6
Q

The _____ that follows a short or near jump is the distance from the next instruction to the jump location.

A

Displacement

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7
Q

jump to the location stored in a memory word

A

Near Indirect Jump

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8
Q

jump to the location stored in a memory doubleword

A

Far Indirect Jump

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9
Q

Are all short jumps that test one or more of the flag bits

A

Conditional Jumps

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10
Q

A special conditional jump instruction that decrements CX and jumps to the label when CX is not 0.

A

LOOP

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11
Q

The _______ instruction jumps if CX is not 0 and if an equal condition exists.

A

LOOPE

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12
Q

The _______ instruction jumps if CX is not 0 and if an not equal condition exists.

A

LOOPNE

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13
Q

are groups of instructions that perform one task and are used from any point in the program.

A

Procedureq

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14
Q

instruction that links to a procedure

A

CALL

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14
Q

instruction that returns from a procedure

A

RET

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15
Q

directive that defined the name and type of procedure

A

PROC

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16
Q

declares the end of the procedure

A

ENDP

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17
Q

is a combination of a PUSH and a JMP instruction

A

CALL

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18
Q

places the contents of IP on the stack

A

Near CALL

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19
Q

places both IP and CS on the stack

A

Far CALL

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20
Q

removes the return address from the stack and placing it into IP

A

Near Return

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21
Q

removes the return address from the stack and placing it into IP and CS

A

Far Return

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22
Q

are either software instructions similar to CALL or hardware signals used to call procedures

A

Interrupts

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23
Q

returns control to the interrupted software

A

IRET

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24
How many interrupt vectors exist in the first 1KB of memory?
256 interrupt vectors
25
How many interrupt vectors are defined by Intel?
32
26
How many interrupt vectors are user interrupts?
224
27
must be used to return from an interrupt service procedure
IRET
28
a conditional interrupt that calls an interrupt service procedure if the overflow flag is 1
INTO
29
tests the condition of the BUSY or TEST pin on the microprocessor
WAIT
30
passes instruction to the numeric coprocessor
ESC
31
compares the contents of any 16 bit register against the contents of two words of memory
BOUND
32
holds local memory variables for the procedure
stack frame
33
creates the stack frame
ENTER
34
removes the stack frame from the stack
LEAVE
35
The ____ clock generator provides the system clock (CLK), READY synchronization, and RESET synchronization
8284A
36
is used by the microprocessor to send the address to the memory or I/O and the ALE signal to the demultiplexers
T1
37
is used to send data to memory for a write and to test the READY pin and activate control signals RD or WR
T2
38
allows the memory time to access data and allows data to be transferred between the microprocessor and the memory or I/O
T3
39
is where data are written
T4
40
A bus cycle that consists of ___ clocking periods act as the basic system timing.
4
41
Stretch the bus cycle by one or more clocking periods to allow the memory and I/O additional access time.
Wait states (Tw)
42
How many combinations can 10 address pins have?
1024
43
is programmed by an EPROM programmer and can be erased if exposed to ultraviolet light
EPROM
44
is programmed in the system by using a 12 V or 5.0 V programming pulse.
Flash Memory (EEPROM)
45
retains data for as long as the system power supply is attached.
Static RAM (SRAM)
46
retains data for only a short period, usually 2โ€“4 ms.
Dynamic RAM (DRAM)
47
3-to-8 line decoder
74LS138
48
2-to-4 line decoder
74LS139
49
The ______ address decoder for microprocessors like the 8088 through the Pentium 4 reduce the number of integrated circuits required to complete a functioning memory system.
PLD
50
Many EPROMs available today have an access time of _______, which is too slow for the 5 MHz 8088. In order to circumvent this problem, a wait state is inserted to increase memory access time to _______.
450 ns, 660 ns
51
________ features are also available for memory systems, but these require the storage of many more bits.
Error-correction
52
The __________ of memory is enabled by the BHE control signal
High Bank
53
The __________ of memory is enabled by the A0 address signal or by the BLE control signal
Low Bank
54
The 8086โ€“Core2 microprocessors have two basic types of I/O instructions:
IN and OUT
55
inputs data from an external I/O device into either the AL (8-bit) or AX (16-bit) register
IN
56
outputs data from AL or AX to an external I/O device and is available as a fixed, variable, or string instruction.
OUT
57
sometimes called direct I/O
Isolated I/O
58
uses a separate map for the I/O space, freeing the entire memory for use by the program.
Isolated I/O
59
uses a portion of the memory space for I/O transfers
Memory-mapped I/O
60
is either built into a programmable peripheral or located separately.
Buffer
61
All input devices are ______ so that the I/O data are connected only to the data bus during the execution of the IN instruction.
buffered
62
All output devices use a _____ to capture output data during the execution of the OUT instruction
latch
63
is the act of two independent devices synchronizing with a few control lines.
Handshaking or Polling
64
are required for most switch-based input devices and for most output devices that are not TTL-compatible
Interfaces
65
decodes only a l6-bit address for variable port instructions and often an 8-bit port number for fixed I/O instructions
I/O port decoder
66
decodes the entire address
Memory Address Decoder
67
is a programmable peripheral interface (PPI) that has 24 I/O pins that are programmable in two groups of 12 pins each (group A and group B).
82C55
68
Mode 0 of 82C55
Simple I/O
69
Mode 1 of 82C55
Strobed I/O
70
Mode 2 of 82C55
Bidirectional I/O
71
The ________ device requires a fair amount of software, but it displays ASCII-coded information
LCD Display
72
The ______ is a programmable interval timer that contains three l6-bit counters that count in binary or binary-coded decimal (BCD)
8254
73
Modes of 8254
0 - Events Counter 1 - retriggerable, monostable multivibrator 2 - pulse generator 3 - square-wave generator 4 - software-triggered pulse generator 5 - hardware-triggered pulse generator
74
The _______ is a programmable communications interface, capable of receiving and transmitting asynchronous serial data
16550
75
The ________ is an 8-bit digital-to-analog converter that converts a digital signal to an analog voltage within 1.0 ฮผs
DAC0830
76
The _______ is an 8-bit analog-to-digital converter that converts an analog signal into a digital signal within 100 ฮผs.
ADC0804