Chapter 9 - (โ๐ฃ๐บ ๐๐ฆ๐ง๐งโ) Flashcards
1
Q
__-pin dual in-line packages
A
40
2
Q
- DIPs
A
o Dual in-line packages
3
Q
- Which microprocessor uses M/IO
A
8086
4
Q
- Which microprocessor uses IO/M
A
8088
5
Q
Power Supply Requirements in Voltage and Tolerance
A
5V +-10% tolerance
6
Q
o 8086 Max current supply
A
360 mA
7
Q
o 8088 Max current supply
A
340 mA
8
Q
Temperature of operation
A
- Between 32 and 180 F
9
Q
Logic 0 V max (input char.)
A
๏ง 0.8 V max
10
Q
Logic 1 V max (input char.)
A
๏ง 2.0 V max
11
Q
Max current (input char.)
A
+- 10uA
12
Q
Logic 0 V max (output char.)
A
๏ง 0.45 V max
13
Q
Logic 0 I max (output char.)
A
๏ง 2.0 mA max
14
Q
Logic 1 V max (output char.)
A
๏ง 2.4 V max
15
Q
Logic 1 I max (output char.)
A
๏ง -400 uA max
16
Q
Pin Connection (8086 & 8088)
o Address/data bus lines are multiplexed address data bus of 8088
A
- AD7 โ AD0
17
Q
Pin Connection (8086 & 8088)
o Address Latch Enable
A
- ALE
18
Q
Pin Connection (8086 & 8088)
o Address bus provides the upper-half memory address bits that are present throughout bus cycle
A
- A15-8
19
Q
Pin Connection (8086 & 8088)
o Address/data bus lines compose the upper multiplexed address/data bus on the 8086
o A15-A8 when ALE is Logic 1
A
- AD15-AD8
20
Q
Pin Connection (8086 & 8088)
o Address/status bus bits are multiplexed to provide address signals A19-A16, S6-S3
A
- A19/S6 โ A16/S3
21
Q
RD
A
Read
22
Q
Pin Connection (8086 & 8088)
o When read signal is L0, data bus is receptive to data from the memory or I/O devices connected
A
- RD
23
Q
Pin Connection (8086 & 8088)
o Insert wait states into the timing of the microprocessor
A
- READY
24
Q
o Request a hardware interrupt
A
- INTR
25
* INTR
o Interrupt request
26
o Input that is tested by the WAIT instruction
* TEST
27
* NMI
o Non-maskable interrupt
28
o Similar to INTR except it does not check to see whether the IF flag is L1
* NMI
29
o Causes the microprocessor to reset itself if this pun is held high for 4 clocking periods
* RESET
30
* CLK
o Clock
31
o Provides the basic timing signal
* CLK
32
o Power supply input provides a 5V, +- 10% signal
* VCC
33
o Return for the power supply
* GND
34
* MN/MX
o Minimum/maximum
35
o Selects either min mode or max mod operation for the microprocessor
* MN/MX
36
* BHE S7
o Bus high enable
37
o Enable the most significant data bus bits during a read or write operation
* BHE S7
38
o Selects memory or I/O
* IO/M (8088) or M/IO (8086)
39
o Indicates that the microprocessor address bus contains either a memory address or an I/O port address
* IO/M (8088) or M/IO (8086)
40
* WR
o Write line
41
o Strobe that indicates that the 8086/8088 is outputting a data to a memory or I/O device
* WR
42
* INTA
o Interrupt acknowledge
43
o Response to the INTR input pin
* INTA
44
* ALE
o Address latch enable
45
o Shows that address/data bus contains address information
* ALE
46
* DT/R
o Data transmit/receive
47
o Shows that the microp data bus is transmitting (DT/R = 1) or receiving (DT/R = 0) data
* DT/R
48
* DEN
o Data enable
49
o Activates external data bus buffers
* DEN
50
o Hold input
o Requests a direct memory access
* HOLD
51
* DMA
o Direct memory access
52
* HLDA
o Hold acknowledge
53
o Indicates that the 8086/8088 has entered the hold state
* HLDA
54
o Equivalent to the So pin in max mode operation of the microp
* SS0
55
o Status bits indicate the function of the current bus cycle
* S2, S1, and S0
56
* RQ/ GT1 and RQ/GT0
o Request/grant pins
57
o Request direct memory access during max mode operation
* RQ/ GT1 and RQ/GT0
58
o Used to lock peripherals off the system
* LOCK
59
* QS1 and QS0
o Queue status
60
o Show the status of the internal instruction queue
* QS1 and QS0
61
* Ancillary component to 8086/8088 microp
8284A Clock Generator
62
* AEN1 and AEN2
o Address enable pins
63
o Provided to qualify the bus ready signals
* AEN1 and AEN2
64
* RDY1 and RDY2
o Bus ready
65
o Provided, in conjunction with AEN1 and AEN2, to cause wait states
* RDY1 and RDY2
66
* X1 and X2
o Crystal oscillator
67
o Connect to an external crystal used as the timing source for the clock generator etc.
* X1 and X2
68
* F/C
o Frequency/crystal
69
o Chooses the clocking source for 8284A
* F/C
70
* CLK
o Clock output
71
o Provides the CLK input signal to the 8086/8088
* CLK
72
* PCLK
o Peripheral clock
73
o One sixth the crystal or EFI input frequency, has 50% duty cycle
* PCLK
74
* OSC
o Oscillator output
75
o TTL-level at same frequency as the crystal or EFI input
* OSC
76
* RES
o Reset input
77
o Active low input to 8284A
* RES
78
o Reset output is connected to the 8086/8088 RESET input pin
* RESET
79
* CSYNC
o Clock synchronization
80
o Used whenever the EFI input provides synchronization in systems with multiple processors
* CSYNC
81
o Connects to ground
* GND
82
o Connects to 5 V +-10% tolerance
* VCC
83
Three buses
o Address bus
o Data bus
o Control bus
84
* Bus cycles = ____ system-clocking periods
four
85
* 8086 __ data bus bits
16
86
* 8088 has __ data bus bits
8
87
* Sampled at end of T2
READY Input
88
* Synchronized ready input to the 8284A clock generator
RDY
89
o Least expensive way to operate the 8086/8088 microp
* Minimum mode operation
90
o Some control signals must be externally generated
* Maximum mode operation
91
o System operated in maximum mode must have this
o Provide the signals eliminated
* 8288 Bus Controller
92
o Connected to the status output pins on the 8086/8088 microp
* S2, S1, and S0
93
o Provides internal timing
* CLK
94
o Demultiplex address/data
* ALE
95
o Controls the bidirectional data bus buffers
* DEN
96
o Output by the 8288 to control the direction of the bidirectional data bus buffers
* DT/R
97
o Causes the 8288 to enable the memory control signals
* AEN
98
o Enables the command output pins on the 8288
* CEN
99
o I/O bus mode input selects either the I/O bus mode or system bus mode operation
* IOB
100
* AIOWC
o Advanced I/O write command
101
o Used to provide I/O with an advanced I/O write control signal
* AIOWC
102
o I/O read command output provides I/O with its read control signal
* IORC
103
o I/O write command output provides I/O with its write control signal
* IOWC
104
* AMWT
o Advanced memory write
105
o Provides memory with an early or advanced write signal
* AMWT
106
* MWTC
o Memory write control
107
o Provides memory with its normal write control signal
* MWTC
108
* MRDC
o Memory read control
109
o Provides memory with its normal read control signal
* MRDC
110
* INTA
o Interrupt acknowledge
111
o Acknowledges an interrupt request input applied to the INTR pin
* INTA
112
* MCE/PDEN
o Master cascade/peripheral data
