𝗖𝗵𝗮𝗽𝘁𝗲𝗿 𝟵: 8086/8088 Hardware Specifications

Question 1

Where are 8086 and 8088 microprocessors packaged in?

Answer 1

dual in-line packages (DIPs)

Question 2

How many pins does dual in-line packages have?

Answer 2

40

Question 3

contain the rightmost 8 bits of the memory address or I/O port number whenever ALE is active or data whenever ALE is inactive.

Answer 3

AD7-AD0; Address/Data Bus

Question 4

provides the upper-half memory address bits that are present throughout a bus cycle

Answer 4

A15-A8; Address Bus

Question 5

Compose the upper multiplexed
address/data bus on the 8086

Answer 5

AD15-AD8; address/data bus

Question 6

Are multiplexed to provide address signals A19-A16 and also status bits S6-S3.

Answer 6

A19/S6-A16/S3; address/status bus

Question 7

Whenever ____ is a logic 0, the data bus is receptive to data from the memory or I/O devices connected to the system.

Answer 7

R̅D̅; read signal

Question 8

is controlled to insert wait states into the timing of the microprocessor.

Answer 8

READY

Question 9

used to request a hardware interrupt

Answer 9

INTR; Interrupt Request

Question 10

Is an input that is tested by the WAIT instruction

Answer 10

T̅E̅S̅T̅

Question 11

INTA

Answer 11

Interrupt Acknowledge

Question 12

Is similar to INTR except that it does not check to see whether the IF flag bit is logic 1

Answer 12

Non-Maskable Interrupt (NMI)

Question 13

causes the microprocessor to reset itself if this pin is held high for a minimum of four clocking periods

Answer 13

RESET

Question 14

provides the basic timing signal to the microprocessor

Answer 14

Clock (CLK)

Question 15

provides a +5.0 V, ±10 % signal to the microprocessor

Answer 15

Voltage Common Collector (VCC)

Question 16

is the return for the power supply

Answer 16

Ground (GND)

Question 17

selects either minimum mode or maximum mode operation for the microprocessor

Answer 17

Minimum/Maximum (MN/M̅X̅)

Question 18

used in the 8086 to enable the most-significant data bus bits (D15–D8) during a read or a write operation

Answer 18

Bus High Enable (B̅H̅E̅ S7)

Question 19

is obtained by connecting
the MN/M̅X̅ pin directly to +5.0 V

Answer 19

Minimum Mode Pins

Question 20

This pin indicates that the microprocessor address bus contains either a memory address or an I/O port address

Answer 20

IO/M̅ or M/I̅O̅

Question 21

is a strobe that indicates that the 8086/8088 is outputting data to a memory or I/O device

Answer 21

Write Line (W̅R̅)

Question 22

is normally used to gate the interrupt vector number onto the data bus in response to an interrupt request

Answer 22

I̅N̅T̅A̅

Question 23

shows that the 8086/8088 address/data bus contains address information

Answer 23

Address Latch Enable (ALE)

Question 24

shows that the microprocessor data bus is transmitting or receiving data

Answer 24

Data Transmit/Receive (DT/R̅)

Question 25

activates external data bus buffers

Answer 25

Data Bus Enable (DEN)

Question 26

If the ____ signal is a logic 1, the microprocessor stops executing software and places its address, data, and control bus at the high-impedance state, if it is a logic 0, the microprocessor executes software normally.

Answer 26

HOLD

Question 27

Indicates that the 8086/8088 has entered the hold state

Answer 27

Hold Acknowledge (HLDA)

Question 28

This signal is combined with IO/M̅ and DT/R̅ to decode the function of the current bus cycle

Answer 28

Single Sign-on (S̅S̅0̅)

Question 29

is obtained by connecting the MN/M̅X̅ pin to ground

Answer 29

Maximum Mode Pins

Question 30

indicate the function of the current bus cycle

Answer 30

Status Bits (S̅2̅, S̅1̅, and S̅0̅)

Question 31

request direct memory accesses during maximum mode operation

Answer 31

Request/Grant (R̅Q̅/G̅T̅1̅ and R̅Q̅/G̅T̅0̅)

Question 32

is used to lock peripherals off the system

Answer 32

L̅O̅C̅K̅

Question 33

show the status of the internal instruction queue

Answer 33

Queue Status (QS₁ and QS₀)

Question 34

is an ancillary component to the 8086/8088 microprocessors

Answer 34

8284A Clock Generator

Question 35

are provided to qualify the bus ready signals, RDY1 and RDY2, respectively

Answer 35

Address Enable (A̅E̅N̅1̅ and A̅E̅N̅2̅)

Question 36

are provided, in conjunction with the A̅E̅N̅1̅ and A̅E̅N̅2̅ pins, to cause wait states in an 8086/8088-based system

Answer 36

Bus Ready (RDY1 and RDY2)

Question 37

selects either one or two stages of synchronization for the RDY1 and RDY2 inputs

Answer 37

Ready Synchronization (A̅S̅Y̅N̅C̅)

Question 38

an output pin that connects to the 8086/8088 READY input

Answer 38

READY

Question 39

connect to an external crystal used as the timing source for the clock generator and all its functions

Answer 39

Crystal Oscillator (X1 and X2)

Question 40

chooses the clocking source for the 8284A

Answer 40

Frequency Crystal (F/C̅)

Question 41

provides the CLK input signal to the 8086/8088 microprocessors and other components in the system

Answer 41

Clock Output (CLK)

Question 42

is one sixth the crystal or EFI input frequency, and has a 50% duty cycle

Answer 42

Peripheral Clock (PCLK)

Question 43

is a TTL-level signal that is at the same frequency as the crystal or EFI input

Answer 43

Oscillator Output (OSC)

Question 44

is often connected to an RC network that provides power-on resetting

Answer 44

Reset Input (R̅E̅S̅)

Question 45

is connected to the 8086/8088 RESET input pin

Answer 45

Reset Output (RESET)

Question 46

is used whenever the EFI input provides synchronization in systems with multiple processors

Answer 46

Clock Synchronization (CSYNC)

Question 47

connects to the ground

Answer 47

GND

Question 48

connects to +5.0 V with a tolerance of ±10%

Answer 48

Power Supply (VCC)

Question 49

If more than 10 unit loads are attached to any bus pin, the entire 8086 or 8088 system must be _____

Answer 49

buffered

Question 50

provides the memory and I/O with the memory address or the I/O port number

Answer 50

Address Bus

Question 51

transfers data between the microprocessor and the memory and I/O in the system

Answer 51

Data Bus

Question 52

provides control signals to the memory and I/O

Answer 52

Control Bus

Question 53

i an extra clocking period, inserted between T2 and T3 to lengthen the bus cycle

Answer 53

Wait State (Tw)