Flashcards in DRAM Deck (45):
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Etching rate of Desired layer/ Etching rate of other layers
Intel Micron Flash Technology
Densification process which enlarges the crystal which decreases the resistance and improves the EM issue
Diamond Like Carbon
(Very erosion resistant and toppling-resistant carbon hardmask film)
Negative Tone Develops
(a photo process where unique developer chemistry removes the unexposed resist. it is used to improve resolution of small contacts or trenches)
Full Etch Back process
Double Pitch Doubling
Dielectric(Deposited) Anti Reflective Coating
Multi Layer Resist
Barrier Low K
Atomic Layer Deposition
(extremely conformal deposition of very thin film)
(Low-density dielectric oxide film, doped with boron and phosphorous, used for filling gaps in topography. Usually deposited very thick)
Bottom Anti-Reflective Coating
(Spin on film applied under photoresist, BARC minimizes substrate reflectivity and planarizes the surface to improve photo pattern integrity)
A method of deposition in CVD that creates a void or airgap in narrow spaces.
Cell Contact, aka Cellcon
(the conductive path from access device to the capacitor in a DRAM cell.
Anti Reflective coating
there are 2 types of anti reflective coating.
BARC and DARC
BARC is spin on (bottom)
DARC is CVD like SiON aka dielectric
Spin of dielectric
A photo process that reduces the printed CD by depositing a second layer on the inside surface of the openings in the resist.
The conductive path from the access device to the digital-line in a DRAM cell. Also known as : Bit Contacts, Bitcon, Digitcon
Double Pitch Doubling
(methods of patterning regular arrays of very small contacts or capacitors)
the process of forming copper interconnects where copper is deposited in trenches, and the surface copper is removed using CMP.
Flowable Chemical Vapor Deposition
(a cvd oxide deposition process where the oxide flows after deposition to round corners and fill void)
Fluorine Resist Etch Stop Coat
(Plasma-based carbon-doped silicon nitride that is resistant to HF. (AMAT trademark)
(The process of removing all the dielectric films used to form the containers in the periphery)
Hexagonal Close Packing
(A hexagonal arrangement of capacitors that optimizes the use of space)
A High Aspect Ratio Process
(A cvd oxide deposition process that can fill narrow gaps with minimal voiding)
High Density Plasma
(A cvd oxide deposition process that produces the high density oxide in narrow tranches)
Insitu Steam Generation
Column to Address Strobe
latency is the amount of time between when information is requested to when it is received.( access time measured in clock cycles)
400 MT/s per DQ (data pin)
(MegaTransfers per Second) A measurement of bus and channel speed in millions of "effective" cycles per second. Also written as "MT/s," it is a rating of the actual, delivered speed rather than the frequency of the clock. For example, if timing is derived from both the rising and falling edges of the cycle rather than one complete cycle, a 400 MHz clock yields 800 MT/sec.
Amount of data per transaction on each data pin. Burs length is programmable. Minimum burst length is set by the prefetch size.
Double Data Rate
(data is sent on the rising and falling edges of the clock cycle)
DQ is Data Pin.
Operating Voltage (Power lines)
VDDQ= powers I/O
VDD= Powers everything els
Voltages for DDR2 and DDR3
DDR2 #standard is 1.8V but also available at 1.5V
DDR3 # Standard is 1.5V but also available at 1.35V and 1.25V
What drives power down?
Technology transitions and Customer demand