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Flashcards in DRAM Deck (45):
1

TWIT

Tapeout Web Interface Tools

2

DI

Deionized (water)

3

Selectivity

Etching rate of Desired layer/ Etching rate of other layers

4

DE

#Design Engineer

#Dry Etch

5

IMFT

Intel Micron Flash Technology

6

CF4

Carbon Tetrafluoride

7

Annealing Proccess

Densification process which enlarges the crystal which decreases the resistance and improves the EM issue

8

DLC

Diamond Like Carbon
(Very erosion resistant and toppling-resistant carbon hardmask film)

9

SP

Scribe Protect

10

NTD

Negative Tone Develops
(a photo process where unique developer chemistry removes the unexposed resist. it is used to improve resolution of small contacts or trenches)

11

TiN

Titanium Nitride

12

FEB

Full Etch Back process

13

DPD

Double Pitch Doubling

14

DARC

Dielectric(Deposited) Anti Reflective Coating

15

MLR

Multi Layer Resist

16

BLoK

Barrier Low K

17

PI

Process Integration

18

ALD

Atomic Layer Deposition
(extremely conformal deposition of very thin film)

19

BPSG

Boro-Phospho-Silicate Glass
(Low-density dielectric oxide film, doped with boron and phosphorous, used for filling gaps in topography. Usually deposited very thick)

20

BARC

Bottom Anti-Reflective Coating
(Spin on film applied under photoresist, BARC minimizes substrate reflectivity and planarizes the surface to improve photo pattern integrity)

21

Breadloaf

A method of deposition in CVD that creates a void or airgap in narrow spaces.

22

CC

Cell Contact, aka Cellcon
(the conductive path from access device to the capacitor in a DRAM cell.

23

Anti Reflective coating

there are 2 types of anti reflective coating.
BARC and DARC
BARC is spin on (bottom)
DARC is CVD like SiON aka dielectric

24

SOD

Spin of dielectric

25

RELACS

A photo process that reduces the printed CD by depositing a second layer on the inside surface of the openings in the resist.

26

DC

The conductive path from the access device to the digital-line in a DRAM cell. Also known as : Bit Contacts, Bitcon, Digitcon

27

DPD

Double Pitch Doubling
(methods of patterning regular arrays of very small contacts or capacitors)

28

Dual Damascene

the process of forming copper interconnects where copper is deposited in trenches, and the surface copper is removed using CMP.

29

FCVD

Flowable Chemical Vapor Deposition
(a cvd oxide deposition process where the oxide flows after deposition to round corners and fill void)

30

FRESCO

Fluorine Resist Etch Stop Coat

(Plasma-based carbon-doped silicon nitride that is resistant to HF. (AMAT trademark)

31

FEB

Full Etchback

(The process of removing all the dielectric films used to form the containers in the periphery)

32

HCP

Hexagonal Close Packing

(A hexagonal arrangement of capacitors that optimizes the use of space)

33

HARP

A High Aspect Ratio Process

(A cvd oxide deposition process that can fill narrow gaps with minimal voiding)

34

HDP

High Density Plasma
(A cvd oxide deposition process that produces the high density oxide in narrow tranches)

35

ISSG

Insitu Steam Generation

36

CAS latency

Column to Address Strobe
latency is the amount of time between when information is requested to when it is received.( access time measured in clock cycles)

37

200Mhz

200M cycles/second

38

DDR2-400

400 MT/s per DQ (data pin)

39

MT/s

(MegaTransfers per Second) A measurement of bus and channel speed in millions of "effective" cycles per second. Also written as "MT/s," it is a rating of the actual, delivered speed rather than the frequency of the clock. For example, if timing is derived from both the rising and falling edges of the cycle rather than one complete cycle, a 400 MHz clock yields 800 MT/sec.

40

Burst Length

Amount of data per transaction on each data pin. Burs length is programmable. Minimum burst length is set by the prefetch size.

41

DDR

Double Data Rate
(data is sent on the rising and falling edges of the clock cycle)
for clk=200Mhz
SDR, DQ=200Mhz
DDR, DQ=400Mhz
DQ is Data Pin.

42

Operating Voltage (Power lines)
VDDQ, VDD

VDDQ= powers I/O
VDD= Powers everything els

43

Voltages for DDR2 and DDR3

DDR2 #standard is 1.8V but also available at 1.5V
DDR3 # Standard is 1.5V but also available at 1.35V and 1.25V

44

What drives power down?

Technology transitions and Customer demand

45

Stand by current leakage?

Leakage caused by fully not-turned off CMOS devices.
AKA "hot devices"