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Flashcards in From Design to Reticle Deck (30):
1

What is Stepping?

Projecting the reticle field several times side-by-side onto the wafer is known as stepping. aka Shots.

2

Why Stepping is needed?

Reticle has small number of die. To fill wafer with die the reticle field needs to be printed multiple times.

3

What is the area allotted for patterns on the reticle?

The maximum area allotted for patterns to be printed on wafer depends on the scanner
field size:
▶ Max. in X direction: 25 to 26 mm (4X on reticle: 100 to 104 mm)
▶ Max. in Y direction: 31 to 33 mm (4X on reticle: 124 to 132 mm)

4

List the two main reticle types typically used in Micron?

Binary and Attenuated Phase Shift Mask (Att PSM)

5

What is a blank?

It refers to the 6" *6" * 1/4" stater material that the mask shop buys with quartz and some other films deposited on it.

6

What films does a binary blank have and what films does an Attenuated Phase Shift Mask blank have?

Binary: Quartz-AR film-resist
Att. PSM: Quartz-MoSi-chrome- AR film - resist

7

What is the purpose of the MoSi in a Att PSM?

MoSi is an attenuated phase shifting material that helps print smaller features by providing better image contrast at the border of a feature, where light passed through the quartz destructively interferes with light that passed through the MoSi.

8

What is GWOT

Great Wall Of Tungsten is a structure placed between the die structures and the scribe structures.

9

what are the purposes of the GWOT?

> Prevent migration of ionic species ( like Na+)
> Provides an equipotential around the die that helps control ground bounce from normal signals and ESD event.
> Mitigates advancing cracks (like thin film cracks) by stopping them or redirecting them away from the die.

10

How have location of GWOT has changed of the time?

Generally prior to 80s it can be found in the outer edge of the die and stagger part only have dummy fills.
In more recent generations part of the GWOT is located in the stagger region and part is located in the die.

11

What is called Level 1 and Level 2 in an Att PSM reticle?

Level 1 is Quartz and MoSi
Level 2 is Level 1 + Chrome

12

What is the purpose of the pellicle ?

The Pellicle film keeps contamination out of the focal plane of the wafer lithography system so it will not image onto the wafer (i.e. the contamination is out of focus so it does not get printed)

13

what is "frm_mask"

It is a merged frame file made up of "mod_frm" and "scb_frm" files

14

What is Barcode frame?

is the part of the reticle that
has patterns not intended to be printed on wafer
▶ Visual ID marks: help operators identify the
reticle
▶ Optical ID marks: help tools identify the reticle
▶ Alignment marks: help scanners align the reticle
▶ Others

15

Who makes the reticles?

Mask shop

16

What is Reticle field?
Or "Field"?

The Reticle Field is the part of the reticle pattern that is intended to print on the wafer.
Examples of patterns found in the Reticle Field:
▶ Die:- example 4 die could be fit (2 in the X direction and 2 in the Y direction). In a production fab these 4 die are identical, in an R&D environment each
of these can be different
▶ Frame or Scribe:- region that separates the die from oneanother; which holds a number of structures like alignment marks, param structures, etc.

17

What Patterns of the reticle get printed on wafer?

Reticle Field (Die and Frame)

18

Reticle Field Efficiency

compactness of the Reticle field. Orientation of the die can be changed to get more die to fit in. ( Reticle-Field / Max. allotted area on reticle to place features to print on wafer)

19

What is a "test-chip"

Test chips may be:
▶ functional: they can be probed and electrical data can be obtained from them or
▶ structural: they are used to develop the process like photo (measure CDs), dry etch,
etc., but no or very limited electrical data can be obtained from them
• An example of a functional test chip is a spider chip (described in the next slide).
• Test chips are not sold to the customers

20

What is a spider chip?

A spider chip is a part where the array has been shrunk from the prior generation, but the periphery is left intact.

21

what are the drawbacks of spider chip?

▶ etch loading and CMP issues may arise in the regions between array and periphery
▶ Periphery may not be optimized for the new array architecture (for example, 66 vs. 68 wordlines), and pitch circuits may not be exactly the same as the Alpha (first shippable) chip.
▶ Periphery process development can be done with a separate non-functional electrical test chip on the same reticle. But may not represent exact configuration on Alpha
▶ Spider wiring directly to array, without new pitch circuits, less successful.

22

What is the Frame?

The reticle field area not
used to pattern the die is called the “frame”, “scribelines”, or “streets”. This is where the parametric test structures,
metrology structures, alignment and registration marks, etc. are found. This space is necessary to allow for a saw to cut or separate the die in assembly. The new standard for all production parts is 90μ frame width (die to die) with some
special exceptions. Test chips may have wider frames.

23

Decipher the Reticle bar code "M49A20A21B-1"

first 4 letter is Design ID (M49A)
Next 2 letter is Level (20)
3 digit A21 A-Die, 2-wavelength, 1 is sizing.
B is Scribe
"-" is mask Designator"
1 is Serial Number

24

What is Stagger?

The buffer zone between Scribe and Die area (same dimension around the die) to keep cracks from propagating. Stagger region can be found in all the frame files.

25

TOAST
(Software)

Tapeout Archive Stream & Test
(takes the snapshots of the die design database at a certain time and archives it)

26

Design to Reticle Data Flow

1. Design Ready, database locked and data base released
2. TOAST – Archive database, stream base stream file
3. TKMASKGEN – dense fill, sized data and mask DRC
4. MFILL – Werner, printable or sub-res Fill, MFILL DRC
5. OPC – Assist features generation, OPC and SiVL check
6. FRACTURE – Mask Data Preparation

27

What is MEBES dimension?

MEBES dimension in microns = GDSII dimension * Shrink Factor * Mask Scale

28

What does pre WARP used for?

Pre WARP tells where it is in the definition and generation process.

29

What does WARP used for?

WARP tell where it is with in the tapeout process.

30

What is called Level 1 and what is called Level 2 in an Att PSM reticle? Identify them in the schematic?

Level 1 :- Contains the layout of the MoSi features
Level2:- MoSi of level 1 is covered by Chrome