Chapter 8: PCI bus subsystems Flashcards Preview

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Flashcards in Chapter 8: PCI bus subsystems Deck (74):
1

Name each coloured arrow for the PCI-X Keying.

Q image thumb

  • 64-bit slot and connector
  • 5V Slot
  • 3.3V slot

2

A single PCI Express serial link is a ____-_______connection

Dual-Simplex

3

PCI adapters that have the ability to gain direct access to system memory are called?

Bus Master Devices

3

The two pair connection in PCI E is called

A Lane

4

PCI-X operates at __ MHz and __MHz.

66 and 133.

5

When supporting previous PCI devices, it is important to note that the clock must scale to a frequency that is acceptable to what?

Lowest speed device on the bus.

5

PCI Express uses a ______ (serial | parallel) interface

Serial

6

Delayed transactions in conventional PCI are replaced by what in PCI-X?

Split Transactions

7

PCI-X has raised the maximum transfer rate in burst mode from 276 MBps to?

4.2GBps

7

PCI E uses two pairs of wires.  What are they used for?

One pair for transmit and oce for Receive.

8

The downside to multi-drop parallel bus is that transactions must include a __________ phase.

Turnaround

9

A basic data transfer operation on the PCI bus is called a PCI

Transaction

10

The generic name for any PCI device is the?

Agent

11

PCI uses a multi-drop parallel bus that is called?

multiplexed address and data bus

12

The benefit of adopting the PCI-X standard is?

The Increased in supported throughputs.

13

Responding PCI Agents are called

Targets

14

All PCI operations are references from

Memory

16

PCI Stands for

Peripheral Component Interconnect

18

PCI-X V2.2 enables a data throughput of over?

4 GBps at 533MHz

19

PCI agents that initiate a bus transfer are called

Initiators

20

The attribute phase takes how many clock cycle(s)?

One

22

The standard PCI bus uses a __ MHz or __ MHz clock

33 or 66

23

PCI-X cards are not designed usually to run at?

100MHz

24

Define PCI

Peripheral Component Interface

25

Define PCI-X

PCI eXtended

26

What two PCI components should be matched for optimal performance

PCI card and PCI bus

27

What kind of bus is the PCI bus

Synchronous Bus

28

What is the MHz of the clock edge

33MHz or 66MHz

29

What are the two possible PCI bus widths

32 or 64 bits

30

PCI uses what type of address bus

Multiplexed address and data bus

31

What phase causes slower data transfers

Turnaround phase

32

What is the theoretical maximum throughput of the standard PCI bus

132MB/s to 528MB/s

33

What is the actual throughput of the standard PCI bus

75% of theoretical (100MB/s to 398Mb/s)

34

What is the purpose of the turnaround phase

Switch from address mode to data mode

35

A PCI device is called

PCI agent

36

A PCI operation is called

PCI transaction

37

The agent that initiates a transfer is called the

Initiator

38

The agent that responds to a transfer is called the

Target

39

PCI uses how many CPU cycles

None (use the front side bus)

40

PCI-X is compatible with traditional PCI on a hardware level (T/F)

True

41

The PCI-X bus is scaled to which PCI device

The slowest

42

List the common PCI-X bus speeds

66MHz 133MHz 133MHz DDR and 133MHz QDR (533MHz possible)

43

Define QDR

Quad Data Rate

44

Describe how QDR works

Separate inputs and outputs that operate at double data rate

45

Why would you use DDR and QDR

To increase performance without increasing clock speed because increasing clock speed uses more energy

46

How many bits are transferred per clock on QDR

2

47

At what points are data transferred in QDR

Rising and falling edges two points in between

48

Define QDR-SPB-SRAM

Quad Data Rate Synchronous Pipeline Burst Static Random Access Memory

49

PCI-X 2.0 supports QDR at what speed

PCI-X 522MHz

50

What is the maximum bandwidth of PCI-X 533

4.26GB/s at 64 bits

51

What is the maximum bandwidth of PCI-X 133

1.06GB/s

52

What are the three PCI-X performance factors

1. Attributes phase 2. Split transaction 3. Allowable disconnect boundary

53

Describe the attributes phase of PCI-X

One extra clock cycle provides more information about the transaction for buffer management

54

Describe the split transactions of PCI-X

Replaces delayed transactions and frees bus for communications

55

Describe the allowable disconnect boundary of PCI-X

Prevents a single process from monopolizing PCI bus with large transfers

56

The PCI-X sequence information identifies what

Total number of bytes remaining to be read or written

57

What happens when a transaction is disconnected

New transaction that continues the sequence includes update byte count

58

Each transaction includes the identity of what

The initiator (bus number device number function number)

59

What does the relaxed order structure allow

PCI-PCI bridges to rearrange the transactions on the bus

60

PCI Express uses what type of interface

Serial

61

PCI Express has how many wire pairs

Two (dual simplex)

62

What are the PCI pairs used for

One transmit pair one receive pair

63

What is a PCI-Express lane

A two wire pair

64

What is a gigatransfer

Raw data rate (bits per second that a bus can move)

65

Encoding overhead takes what percent of the GT/second speed

20%

66

8GT/sec translates to what

6.4GT/sec of useful data (6.4GB/sec or 800Mb/sec)

67

PCI-E is compatible with traditional PCI on a hardware level (T/F)

False

68

PCI-E is compatible with traditional PCI on a software level (T/F)

True

69

PCI-to-PCI briges allow for what

Multiple speeds of PCI buses at once

70

The PCI-to-PCI bridge interface is located where

In the memory controller

71

What part of the PCI-E connectors does not need to be managed the same was as PCI or PCI-X

The bandwidth

72

What kind of connection is PCI-Express

Point-to-Point

73

Point-to-point connection of PCI-E is a what

Switched fabric for high performance

74

The combined speed of PCI-X edge connectors cannot exceed what

Allocated bandwidth between memory controller and PCI bridge