Chapter 9: Chipset

Question 1

System and chip designers generally use a key metric known as

Answer 1

Cycles Per Instruction (CPI)

Question 2

CPIs are used to measure the number of what?

Answer 2

Processor Clocks that system uses to execute an instruction.

Question 3

While the number of instructions to execute an operating is held constant, the number of what decreases?

Answer 3

The number of cycles.

Question 4

Chipset defines operation of what types of devices?

Answer 4

PCI, SATA, USB, RAID, and more.

Question 5

The chipset optimizes operation of what?

Answer 5

The CPU

Question 6

Controls data flow between what components?

Answer 6

Processor, memory, PCI devices, and system bus.

Question 7

All access to the CPU is controlled through the?

Answer 7

Chipset

Question 8

To minimize performance bottlenecks, you want to match the right chipset with the right?

Answer 8

CPU

Question 9

Decreasing the cycles required to process an operation, combined with what increases system performance?

Answer 9

Higher clock rate

Question 10

Servers have what type of workload?

Answer 10

Random

Question 11

What depends on the chipset to quickly transfer information from main memory?

Answer 11

The CPU

Question 12

The two multi-processor architectures available in System X servers are?

Answer 12

SMP and NUMA

Question 13

SMP stands for?

Answer 13

Symmetric Multiprocessing

Question 14

When using SMP, what does each CPU “see”?

Answer 14

The same hardware resources

Question 15

What is one disadvantage to SMP?

Answer 15

Limited scalability

Question 16

NUMA stands for?

Answer 16

Non-uniform memory access

Question 17

True / False: NUMA is only for memory?

Answer 17

False, NUMA can also access I/O resources

Question 18

In NUMA, every processor or group of processors has a certain amount of what?

Answer 18

Memory Local to It

Question 19

The primary difference between NUMA and SMP is?

Answer 19

NUMA has multiple memory subsystems.

Question 20

What is SRAT?

Answer 20

Static Resource Allocation Table

Question 21

AMDs version of SRAT is?

Answer 21

SUMO - Sufficiently Uniform Memory Organization

Question 22

What is a complicating factor for the design of any SMP system?

Answer 22

The need to keep all CPU and cache data coherent.

Question 23

A protocol called ____ is employed on all Intel multi-processor configurations to ensure that each CPU is guaranteed to get the most recent copy of data even when other CPUs are currently using that data.

Answer 23

MESI

Question 24

MESI stands for?

Answer 24

Modified, Exclusive, Shared, Invalid.

Question 25

To support the MESI protocol, regular communication must occur between every ___ whenever data is loaded into a cache.

Answer 25

CPU

Question 26

Snoop Cycles occur when?

Answer 26

Every memory read or write operation

Question 27

If the operation is a SMP write request, the CPU that possesses the unmodified data must mark its data as?

Answer 27

Invalid

Question 28

If the operation is a SMP read request, the CPU that possesses the unmodified data must mark its data as?

Answer 28

Shared

Question 29

AMD uses a slightly different version of MESI called?

Answer 29

MOESI

Question 30

The primary difference between MESI and MOESI is?

Answer 30

The owner statis flag

Question 31

The larger the L2 cache, the greater the probability that _____ requests will hit data in another processor cache.

Answer 31

snoop

Question 32

The Intel front-side bus protocol is limited to how many processor sockets.

Answer 32

Four

Question 33

What is UEFI?

Answer 33

Unified Extensible Firmware Interface

Question 34

What replaced BIOS after nearly 20 years?

Answer 34

UEFI

Question 35

In opteron processors, the processor and ______ _________ logic are integrated into the same piece of silicon.

Answer 35

Memory Controller

Question 36

When four processors are placed at the edges of a square, what type of remote access occurs?

Answer 36

two-hop remote memory access