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Flashcards in Midterm Deck (35):
1

How does a server chipset act to control system-wide latency?

Controls the data flow between the CPU, caches, and memory.

2

Matching the server chipset to the server CPU helps to minimize what?

Bottlenecks

3

In servers the two commonly used multi-processor architectures are? (No acronyms)

Symmetric Multiprocessing, Non-Uniform Memory Access

4

The acronym PCI stands for what?

Peripheral Component Interface / Interconnect

5

IBM refers to the PCI bus as what?

Multiplex address and data bus

6

What is the PCI turnaround phase?

The transition from Data mode to address mode, or visa versa.

7

Most IBM X System Servers have replaced PCI-X with what?

PCI Express

8

QDR transfers how many data bit per clock cycle?

4

9

A PCI Express Serial link uses two wire pairs, what is the role of each pair?

One to send and one to receive

10

PCI Express devices look like what types of devices to software?

PCI devices

11

What is the major design difference between PCI-E and the previous versions of PCI?

PCI-Express is serial, everything else is parallel.

12

According to Moores Law the numbers of transistors in CPUs doubles how many years?

Every 2

13

The acronym UEFI stands for what?

Unified Extensible Firmware Interface

14

UEFI was originally designed for what processor?

Itanium

15

UEFI was designed to replace what in a server?

BIOS

16

What does UEFI component testing eliminate?

Beep Codes

17

What was the first version of Windows Server to support UEFI?

2008

18

Under virtualization what normally runs under privilege level 3?

Applications

19

Under virtualization what normally runs under privilege level 0?

Virtualization layer

20

What is the role of the hypervisor?

Allows multiple OS’ to run on a single host?

21

What does binary translation address?

Ring deprivileging

22

There are three hardware requirements for virtualization, one is hypervisor support, one is BIOS support, what is the third?

CPU support

23

The acronym ACPI stands for what?

Advance configuration power interface

24

How does the P state differ from the T state?

P state addresses the clock rate and the T state addresses how many clock ticks the CPU will respond to

25

The NIC receive frame command contains what things requires to store the receive frames contents?

Receive Instruction and the Address

26

What type of server has a primary function of storing, searching, retrieving, and updating data?

Database server

27

What is often because of major bottlenecks in a DNS server?

The NIC

28

Explain the difference between active memory and MXT?

Active memory mirrors the memory, while MXT compresses it.

29

An average enterprise uses what percent of a server's capacity?

20%

30

The ability to change P-States is an ability Intel calls what?

Demand Based Switching

31

Same question but for AMD?

PowerNow!

32

What is the effect of increased cache size on the speed of main memory access?

Slows it down

33

What is the most frequently access server hardware resource?

Memory

34

AMD uses HyperTransport together with that other technology to group processors?

SUMO

35

AMD uses three HyperTransport links to connect the opteron what is each link used for?

Two to connect to connect to CPU, Third for I/O.