Memory Flashcards

Week 5 - 10 (43 cards)

1
Q

what is the main memory trade-off

A

capacity vs cost per bit vs access time

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2
Q

what are the 3 performance parameters

A
  1. access time
  2. memory cycle time
  3. transfer rate
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3
Q

what is the access time

A

time between presenting the address and recieving or storing the valid data

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4
Q

what is the memory cycle time

A

access time + recovery time

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5
Q

what is the transfer rate

A

the rate at which data can be moved

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6
Q

what is a unit of transfer

A

number of data lines into and out of a memory module

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7
Q

what is the internal unit of transfer

A

data bus width

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8
Q

what is the external unit of transfer

A

block

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9
Q

what is an addressable unit

A

smallest location which can be uniquely addressed

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10
Q

how does sequentiual access access memory

A

starts at the beginning of the memory and accesses records in order

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11
Q

what are the 3 ways to access memory

A
  1. sequential
  2. direct
  3. random
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12
Q

how is access time determined in sequential access

A

depends on the location of the data & the previous location
- highly variable

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13
Q

how does direct access access memory

A

moves to a general region of memory then uses sequential access

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14
Q

how is access time determined in direct access

A
  • indiviual blocks have unique addresses
  • still depends on location and previous location
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15
Q

how does random access access memory

A

allows any selected memory location to be directly addressed and accessed

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16
Q

how is access time determined in random access

A
  • independent of location of previous access
  • unique physical address identifies locations exactly
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17
Q

what are the 3 types of storage

A
  1. semiconductor
  2. magnetic
  3. optical
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18
Q

4 physical characteristics of memory

A
  1. information can decay naturally or be lost without electrical power
  2. volatile/non-volatile
  3. non-readable memory cannot be altered - ROM
  4. power consumption - influences cost
19
Q

describe RAM

A
  • read/write
  • volatile - useful for temporary storage
  • can be static or dynamic
20
Q

describe dynamic RAM

A
  • periodically refreshes cells as charges can leak, even when powered
  • simpler & smaller
  • denser & v expense
  • suited to large memory requirements
  • requires a refresh option - chip disabled while refreshing
21
Q

describe static RAM

A
  • cells store bits using the same on/off logic elements used in the processor, no charges to leak so no refreshing needed
  • requires less circuitry
  • faster
  • suited for cache
22
Q

describe ROM

A
  • provides permanent data which cannot be changed
  • non-volatile
23
Q

what are the 2 types of memory errors

24
Q

what is a hard failure

A

permanent physical affects

25
what is a soft failure
random events alter the stored information but no permanent damage
26
how can memory failures be detected & corrected
1. parity bits 2. hamming codes
27
describe parity bits
- to detect errors in data communication and processing, an additional bit is sometimes added to a binary code word to define its parity - a parity bit is the extra bit included to make the total number 1's in the resulting code word either even or odd
28
how are parity bits generated & checked
- an even bit is generated at the sending end for all 7-bit ASCII characters - 8-bit characters including the parity bits are transmitted to their destination - Parity of each character is then checked at the receiving end - if the parity of the received character is not even (assuming even parity is used), at least one bit has changed its value during transmission
29
pro of parity bits
uses only a single bit, resulting in the least overhead
30
cons of parity bits
- if the number of changes is even, the error will not be detected - it can only detect 1, 3, or any odd number of errors in each character - parity does not indicate which bit contained the error - only detect - data must be discarded enitrely, and retransmitted from scratch
31
describe hamming codes
- k parity bits are added to an n-bit data word, forming a new word of n + k bits - those positions numbered with powers of 2 are reserved for parity bits - code can be used with words of any length
32
how is an additional parity bit used with hamming codes
- extra parity bit applies to all bits after the hamming code check bits have been added - then all single-bit, two-bit & three-bit errors can be detected
33
how does an additional parity bit with hamming codes distinguish even-bit errors
- no parity error is detected - hamming code indicates there is an error - hamming codes are capable of correcting an error or detecting 2 but not capable of doing both simultaneously
34
hamming code rule
d + p + 1 <= 2^p - where d = data bits, p = parity bits
35
how are hamming codes checked
- when the 12 bits are read from emory, they are checked again for errors - C = C8C4C2C1 - C1 = XOR(1, 3, 5, 7, 9, 11) - C2 = XOR(2, 3, 6, 7, 10, 11) - C4 = XOR(4, 5, 6, 7, 12) - C8 = XOR(8, 9, 10, 11, 12) - if C = 0, there is no error detected - if C != 0, the 4 bit vinary number formed by the check bits gives the postion of the erroneous bit if only a single bit is in error
36
what causes hard failures
- harsh environment - manufacturing defect - wear & tear
37
what causes soft failures
- power supply issues - alpha particles
38
draw a venn diagram for 4-bits and 3-parity bits
39
what are syndromes
partity bits XOR with their own bits - i.e - Pa XOR b2 XOR b1 XOR b0
40
if SEC is 0 this indicates
no error
41
if SEC is 1 this indicates
error in check bit
42
if SEC is >= 2 this indicates
error in data bit
43
what is the formula for the number of bits needed for SEC codes
2^k - 1 >= M + k where: - M = num data bits - k = num parity bits