Architecture & Components Flashcards
Week 1, 5-10 (33 cards)
define architecture
attributes of a system, direct impact on logical execution
define organisation
how the architecture is implemented
define structural
the way the components relate to each other - hierachical
define function
operation of individual components
name the main 5 components of a computer
- CPU
- main memory
- I/O
- system bus
- co-processors
name the 4 main components of the CPU
- control unit
- ALU
- registers
- interconnection
what does the CPU do
controls operation, FDE cycle
what does the control unit do
controls operation of CPU
what does main memory do
stores data and program instructions
what does I/O allow
allows machines to gain information and interact with the users and other devices
what is the cache
smaller, faster, located closer to the CPU, stores frequently used instructions & data
3 components of a multicore
- CPU
- Core - individual processing unit
- processor - contains one or more cores
what are switches & how are they used in computers
- two states, easy to map logical states
- allows for boolean logic to be performed
- binary arithmetic
- storage of data in binary form
what is von nuemann architecture
- data & instructions stored in same single read-memory
- content of this memory are addressable by location
name the 7 main registers
- MAR
- MDR
- CIR/IR
- PC
- MBR
- AC & MQ (Multiplier Quotient)
- IBR
what does the MBR do
contains a word to be stored in memory or sent to the I/O unit OR is used to receive a word from memory or form I/O unit
what does the IBR do
temporarily hold the right hand instruction from a word memory
what is the opcode
code for instruction to perform
what is the operand
data to perform instruction or address to use
3 instruction types
- data handling
- arithmetic & logic
- control flow
describe the FDE cycle
- Fetch
- opcode of the next instruction is loaded in to IR
- address portion is loaded into the MAR
- data portion is loaded into the MDR - Decode
- decodes instruction - Execute
- interprets opcode as control signals
- sends out control signals to cause data to be moved or an operation to be performed by ALU
describe the von neumann bottleneck
- shares memory bus for data and program instructions
- single bus limits throughput between CPU and memory
- CPU must wait for data to be moved to or from memory
mitigations for the von neumann bottleneck
- cache between CPU & main memory
- seperate caches or seperate access paths for data & instructions
- on-chip scratchpad memory to reduce memory access
- implementing the CPU & memory hierarchy as a system on chip - greater locality of reference = v latency
define harvard architecture
- difference = 2 buses = memory & data
- ADV: CPU recieves instruction & data concurrently
- DIS: programs cannot be stored in same memory as data
- uses: microcontrollers, digital signal process