Mulitcore Systems

Question 1

what are the 3 drivers of growth in microprocessor performance

Answer 1

1. higher clock frequency
2. increased transistor density
3. smarter on-chip architecture designs

Question 2

what 3 things are now used in processor designs to exploit ILP

Answer 2

1. pipelining
2. superscalar
3. SMT

Question 3

describe pipelining

Answer 3

• enables overlapping of instructions
• while one instruction is in one stage, another can occupy a different stage
• increases instruction throughput and performance

Question 4

limit of pipeling

Answer 4

deeper pipelines requrie more controlo & logic, with diminishing returns

Question 5

describe superscalar

Answer 5

• replicate execution units to create multiple pipelines
• multiple instructions are issued and executed in parallel during each instruction cycle
• parallelism is limited by instruction dependencies

Question 6

limit of superscalar

Answer 6

code rarely offers parallelism beyond 6 pipelines

Question 7

describe SMT

Answer 7

• allows multiple threads to share pipeline resources within a single core
• instructions from different threads can be issues in the same cycle

Question 8

limit of SMT

Answer 8

complexity in scheduling and resource sharing limits scalability

Question 9

describe the affect of icnreasing clock speeds & complexity on power consumption

Answer 9

^ clock speed & added complexity = ^ power density

Question 10

what is the response to rising power density

Answer 10

^ on-chip cache memory as it consumes less power than logic

Question 11

what does multicore offer in terms of performance

Answer 11

if software is parallelisable = near-linear performance
- large caches are underutilised by single threads
- multiple cores and threads better exploit on-chip cache memory

Question 12

what does amdahl’s law represent

Answer 12

theoretical speedup for a single application on N cores

Question 13

amdhal’s law formula

Answer 13

Speedup(N) = 1/((1 - f) + f/N)
where:
- f = fraction of the program that is parallelisable
- 1 - f = fraction that is inherently sequential

Question 14

what does amdhal’s law assume

Answer 14

perfect parallelism with no scheduling overhead

Question 15

what is a more realisitc assuption about amdahl’s law

Answer 15

as core count increases, ^ overhead = peak & degrade

Question 16

4 applications that scale well with multicore systems

Answer 16

1. multithreaded native apps
2. multiprocess applications
3. java applicationds
4. multi-instance applications

Question 17

define threading granularity

Answer 17

refers to the smallest unity of work that can be parallelised

Question 18

what does fine-grained threading give

Answer 18

flexibility
- BUT ^ overhead from managment

Question 19

trade off of threading granularity

Answer 19

parallelism vs overhead

Question 20

what does rendering use

Answer 20

hierarchical thread structure

Question 21

what are the 4 multicore cache organisations

Answer 21

1. dedicated L1 cache
2. dedicated L2 cache
3. shared L2 cache
4. shared L3 cache

Question 22

5 advantages of shared higher-level cache

Answer 22

1. constructive interface
2. no data repliction needed
3. dynmaic cache allocation
4. easier inter-core communication
5. simplified coherency

Question 23

why is a constructive interface an advantage of shared higher-level cache

Answer 23

threads on different cores benefit from shared data already located in cache

Question 24

why is dynamic cache allocation an advantage of shared higher-level cache

Answer 24

cores can use more or less cache depending on workload needs

Question 25

why is simplified coherency an advantage of shared higher-level cache

Answer 25

coherence issues are limited to private (lower-level) caches, reducing overhead

Question 26

what is the trend in cache hierachy design

Answer 26

as you ^ memory capacity and core counts = ^ importance of cache coherency

Question 27

new cache hierachy design

Answer 27

L1 per core, L2 shared among 2-4 cores, and global shared L3

Question 28

why is SMT deployed in multicore design

Answer 28

- SMT increases the number of hardware threads per chip - as software becomes more parallel, SMT becomes more attractive than purely superscalar designs

Question 29

define homogenous multicore

Answer 29

all cores are identical

Question 30

define heterogenous multicore

Answer 30

differnt types of cores on one chip - mixing cores in this context means using cores with differnt ISAs optimised for different tasks

Question 31

describe CPU/GPU multicore

Answer 31

- GPUs - support thousands of parallel threads. - combining CPUs & GPUs improve flexibility & performance across diverse workloads - CPUs & GPUs share key-on-chip resources such as last level cache, interconnect & memory controllers

Question 32

what are the 2 solutions to CPU/GPU cache issues

Answer 32

1. physical memory partitioned between CPU & GPU 2. enabling shared access to memory & unified expression

Question 32

how does physical memory paritioned between CPU & GPU work

Answer 32

- CPU had to explicitly copy memory to GPU memory - GPU copied results back after computation - significant performance penalty

Question 32

what are the 2 challenges with CPU/GPU multicore

Answer 32

1. ensuring coordination & correctness between different types of cores 2. cache sharing - differences in access patterns & sensitivity

Question 33

how does enabling shared access to memory & unified execution work

Answer 33

- shared virtual memory - demand paging - cache coherence - unified programming interface

Question 34

describe CPU/DSP multicore

Answer 34

DSP - excel at ultra-fast, math-intensive operations

Question 35

uses of CPU/DSP

Answer 35

- cellphones - modems - sound cards - hard drives

Question 36

desribe ARM big.LITTLE architecture

Answer 36

- cortex-A15: high performance for intensive tasks - cortex-A7: power-efficient for light tasks - designed for smartphones & tablets - use low-power cores most of the time, and switch to high performance cores when needed - extends battery life while still meeting user performance expectations

Question 37

describe Cortex A-15

Answer 37

- out-of-order, superscalar processor - pipeline length - 15-24 stages - 3 instructions per cycle - 8 execution units each with its own queue

Question 38

describe Cortex-A7

Answer 38

- simpler, energy efficient in-order processor - pipeline length - 8-10 stages - uses a single queue - supports dual-issue: 2 instructions per cycle - low transistor count - low power consumption

Question 39

describe cache design in heterogenous multicore systems

Answer 39

use dedicated L2 caches per processor type - hardware-based cache coherence preferred in SoCs

Question 40

describe Intel Core i7 architecture

Answer 40

- 6-core processor with each core having a private L2 cache - all cores share a 12 MB L3 cache - uses hardware prefetching - integrated DDR3 memory controller - uses QPI

Question 41

describe Cortex-A15 MPCore

Answer 41

- high-performance applications - homogenous multicore processor with multiple A15 cores

Question 42

how does interrupt handling occur in Cortex-A15 MPCore

Answer 42

- Generic Interrupt Controller manages & routes interrupts to A15 cores and is accessed by each core via the SCU ○ mask and prioritise interrupts ○ route interrupts to one or more CPUs ○ track interrupt status ○ generate interrupts via software - interrupt distributor sends highest-priority pending interrupt to each CPU interface - CPU interface sends ○ acknowledge signal ○ end of interrupt

Question 43

describe cache coherency in Cortex-A15 MPCore

Answer 43

- L1 cache coherence is maintained using the MESI protocol by the SCU - L2 cache coherence uses a hybrid MESI/MOESI protocol

Question 44

describe the multichip module (MCM) in IDM EC12

Answer 44

integrates 6 high-speed processor units, each with 4 cores & 2 storage control chips for interconnection to other MCMs

Question 45

describe the four-level cache architecture in IDM EC12

Answer 45

- L1 & l2 caches are private & use write-through policy - L3 shared for high capacity & fault tolerance - L4 cache (on SC chips) acts as a coherence manager

Question 46

what is IDM EC12 best sutied for

Answer 46

- suited for transaction-heavy workloads with high data sharing & context switching - prioritises minimising main memory access by maximising on-chip cache