Cache & Internal Memory

Question 1

name the 7 elements of cache design

Answer 1

1. cache replacment
2. write policy
3. replacement algorithms
4. number of cores
5. line size
6. cache size
7. cache addresses

Question 2

what are the three cache write policies

Answer 2

1. cache replacement
2. write through policy
3. write back policy

Question 3

what is the cache replacement write policy

Answer 3

• unaltered blocks can be overwritten without updating main memory
• modified blocks must be written back to main memory replacement

Question 4

what is the write through policy

Answer 4

• updates cache & main memory for consistency
• the word being written is updated in cache & memory

Question 5

advantages of write through polic

Answer 5

simplifies consistency in multi-device systems

Question 6

disadvantages of write through policy

Answer 6

high memory traffic, potential bottlenecks

Question 7

what is the cache write back policy

Answer 7

• updates only when the block is replaced
• the entire block is updated even if one single word has changed

Question 8

advantages of the cache write back policy

Answer 8

v memory traffic

Question 9

disadvantages of the cache write back policy

Answer 9

complex handling to avoid memory states

Question 10

what types of mapping need to replacement algorithms

Answer 10

• associative
• set-associative

Question 11

what are the 3 replacement algorithms

Answer 11

1. least recently used
2. FIFO
3. least frequently used

Question 12

how does the least recently used algorithm work

Answer 12

replaces the block unused for the longest time

Question 13

how does the least frequently used replacement algorithm work

Answer 13

replaces block with the fewest references

Question 14

what is split cache

Answer 14

seperate cache fore instuctions & data

Question 15

advanatage of split cache

Answer 15

avoids contention
- essential for superscalar machines

Question 16

advantage of unified cache

Answer 16

^ hit ratio & simple implemetatin & design

Question 17

describe how changing the block size affects cache

Answer 17

• ^ block size fetch adjacent words = ^ hit ratio
• large blocks
  = v blocks that can fit in cache
  = additional words are further from the requesred block size

Question 18

what is the problem with cache coherency in multi-processor systems

Answer 18

altering data in one cache can invalidate corresponding data in main memory & copies in other caches

Question 19

what is are the 3 solutions to cachecoherency in multi-processor systems

Answer 19

1. bus watching
2. hardware transparency
3. noncacheable memory

Question 20

what is bus watching

Answer 20

• cache controllers monitor writes to shared memory
• invalidate matching cache entries when changes are detected
• CPU next time must fetch the updated value from memory

Question 21

what is hardware transparency

Answer 21

if a processor modifies a word in its cache, the update is written to memory & propagated to matching other caches

Question 22

what is non cacheable memory

Answer 22

• shared memory is never stored in cache, so all accesses result in cache misses
• special hardware marks shared memory as noncacheable

Question 23

structure of static RAM

Answer 23

• uses flip-flop logic-gate configurations
• no need for refresh as long as power is supplied

Question 24

define operations of SRAM

Answer 24

1. WRITE - bit value is applied to force transistors into the correct state
2. READ - bit value is read from the designated line

Question 25

characteristics of SRAM

Answer 25

- faster than DRAM - ^ cell size = v density = ^ cost - used for cache

Question 26

structure of DRAM

Answer 26

- stores data as charge on capacitors - requires periodic refreshing by memory controller due to charge leakage

Question 27

operations with DRAM

Answer 27

- WRITE - voltage applied to the bit line charges the capacitor - READ - charge must be transferred to a sense amplifier and must be restored

Question 28

characteristics of DRAM

Answer 28

- simple & small cells -> high density -> cost-effective - slower than SRAM due to refresh overhead - commonly used for main memory

Question 29

describe traditional DRAM

Answer 29

- asynchronous: processor sends addresses and control signals to the DRAM and is idle during this time - during the delay (access time) DRAM: - activates row & column to locate the specific memory cell - senses the charge - 1 0=or 9 - routes data to/from the processor via output buffers

Question 30

describe SDRAM

Answer 30

- operates in syncwith an external clock signal - instructions & address information are latched by the SDRAM, which processes the request in a set number of clock cycles - allows the processor to perform other tasks while SDRAM handles the memory request

Question 31

describe DDR RAM

Answer 31

an enhanced version of SDRAM that increases I/O data rate - uses a prefetch buffer

Question 32

how and why is a prefetch buffer implemented in DDR RAM

Answer 32

- the prefetch buffer in DDR preloads multiple words from slow DRAM, ensuring fast, continuous data transfer to the CPU - The MUX in DDR ensures that prefetched words are sent in the correct, order by assigning them to the rising and failing edges of the clock for smooth, sequential data transfer.

Question 33

what are the prefetch challanges of DDR4

Answer 33

- larger prefetch sizes complicate short bursts - increasing buffer size to 16 bits was inefficent for DDR4

Question 34

describe using bank groups in DDR4 DRAM

Answer 34

- DDR4 DRAM is divided into bank groups, each functionality independently - this allows the memory controller to send commands to multiple groups simultaneously, enabling parallel operations - DDR4 supports up to 4 bank groups, improving throughput