Interconnection Structure Flashcards
Week 2.7 (57 cards)
1
Q
describe interconnection as a computer component
A
- the way these components are interconnected defines performance, efficiency & scalability
- a well-designed interconnection structure minimises bottlenecks and enhances reliabiltiy
2
Q
describe the hardwired configuration
A
- fixed arrangement of logic components designed for specific computation
- ‘program’ is built into hardware
- changing computation requires physicall modifying the circuit
3
Q
characteristics of a hardwir3ed configuration
A
- optimised for speed & efficiency in a dedicated tabke
- lacks flexibility
- used in applications requiring high-performance fixed computations
4
Q
describe general-purpose configuation
A
- a flexible set of arithmetic and logic functions controlled by external signals
- the same hardware can perform multiple computations by changing control inputs
- instead of rewiring hardware, control signals determine which operation is performed
5
Q
characterisitcs of a general-purpose configuration
A
- programs executed as a sequence of steps, each requiring a new set of control signals
- control unit decodes & generates required control signals
- enables programmable computing - modern processors
6
Q
define the instruction register
A
stores the fetched instruction, which the processor decodes & executes
7
Q
what 4 actions can an instruction perform
A
- processor-memory
- processor-I/O devices
- data processing - arihtmetic or logic operations
- control - alter the sequency of execution
8
Q
describe interrupts
A
- allow I/O and memory modules to signal the processor, temporarily halting normal execution
- reduces CPU idle time - no waiting for slower devices
- no interrupts = waiting for external devices to catch up
9
Q
what are the 4 classes of interrupts
A
- program
- timer
- I/O
- hardware failure
10
Q
what is a program interrupt
A
- generated by conditions occuring during instruction execution
- arithmetic overflow, division by 0, illegal instruction execution, memory access violation
11
Q
what is a timer interrupt
A
triggered by a processor time, allowing the operating system to perform periodic tasks
12
Q
what is a I/O interrupt
A
generated by an I/O controller to signal operation completion, request processor service or indicate errors
13
Q
what is a hardware failure
A
caused by system failure such as power loss or memory parity errors
14
Q
what does I/O execution look like without interupts
A
CPU processing blocked while waiting for the I/O to complete = inefficient
15
Q
define interrupt handling
A
temporairly hold execution but the program resumes from the same point eithout special handling
16
Q
describe the interrupt cycle process
A
- interrupt cycle added to the instruction cycle
- if an interrupt occurs:
○ the processor suspends execution and saves its current context
○ program counter is updated to the interrupt handler’s address
○ interrupt handler executes, determines the cause, and services the interrupt
○ once complete, execution resumes from where it was interrupted - introduces processing overhead but allows efficient task management
17
Q
what are the 2 ways handling multiple interrupts
A
- sequential processing
- nested processing
18
Q
describe sequential processing
A
- when an interrupt occurs, the processor disables further interrupts until the handler completes
- any pending interrupts remain and are checked after re-enabling interrupts
- ignores priorty = data loss
19
Q
define nested processing
A
high-priority interrupts can interrupt low-priority handlers, ensuring urgent tasks are addressed for
20
Q
describe exchanges for memory module
A
- a memory consists of N words of equal length, each with a unique address
- data can be read from or written into the memory based on control signals
- R & W operations specify the target address
21
Q
describe exchanges for CPU module
A
- read instructions & data from memory
- write out process data
- uses control signals to manage system operations
- responds to interrupt signals
22
Q
describe exchanges for the I/O module
A
- I/O operations - R & W functions
- can control multiple external devices via ports
- data transfer occurs through external data parts for I/O
- I/O modules can send interrupts
23
Q
what are the 2 structures of interconnection
A
- bus interconnection
- point-to-point
24
Q
describe bus interconnection
A
- dominant method
- bus = shared communciation pathway connecting major components
- only one device can transmit a single at a time to avoid conflicts
- consists of multiple lines: data, address & control groups)
- several lines can transmit data in parallel, ^ speed
25
describe the data bus
- width = how many bits can be transferred at a time
- ^ width = ^ performance
as v memory access cycles needed for large instructions
26
describe the address bus
- specifies the source or destination of the data bus
- higher-order address bits select a memory or I/O module
- lower-order bits specify locations within the module
- width = determines maximum memory capacity & also addresses I/O parts
27
describe the control bus
- manage access to shared address & data buses, ensuring orderly communication
- include command & timing signals
- to send or request data, a module must first gain bus access and then transfer data or request through control and address lines
28
what was the challenge with bus interconnection
- ^ bus frequency creates electrical constraints
- multicore chips magnify bus limitations - ^ latency & v data rates
29
what was the solution to tghe challenges with bus interconnection
P2P
- v latency & ^ data rate
- ^ scalability
30
describe QPI
- shared DRAM access - accessed through separate memory controllers
- 3 types of interconnction
- the IoH manaages data transfer between cores & peripheral devices, connecting to I/O devices via PCIe and translates protocols
- enables scalable designs by routing through intermediate processors
31
what are the 3 types of interconnection in QPI
1. memory bus
2. QPI links
3. PCI express
32
define the memory bus in QPI
connects each core's memory controller to DRAM for direct access
33
defibe QPI links
connects cores to each other and to the I/O hub for cache coherency and inter-core communication
34
define PCIe in QPI
connects I/O hub to I/O devices such as GPUs, storage & netowrking commponents
35
key characteristics of QPI
- direct connection allow cores to communicate independently, avoiding delays from shared bus access
- layered protocol architecture similar to network protocols
- packetised data transfer with control headers and error control codes
36
what are the 4 protocol layers of QPI
1. protocol layer
2. routing layer
3. link layer
4. physical layer
37
descibe the protocol layer in QPI
defines:
- the data types & format, which consists of multiple flits
- type of transcation
- what type of response is needed
- ensures special rules are followed
38
describe the routing layer in QPI
determines the path between nodes in cases where multiple routes exist
- packet traversal path across system interconnects through routing tables
- reads packet headers to either process it or forward to next destination
- adjusts dynamically based on system configuration, resource partitioning or hardware failures
39
describe the link layer in QPI
ensures reliable data transfer & flow control using 80-bit flits
- flow control to prevent overwhelming the reciever
- credit scheme to manage data transmission pace
- error control using an 8-bit CRC for each flit
- flit = 8-bit CRC & 72-bit payload
40
describe the physical layer in QPI
handles signal transmission and reception, transferring data in 20-bit phits
- port consists of 84 individual links grouped into transmit & recieve lanes
- each data path has a pair of wires (lane) transmititng data one bit at a tome
- uses low-voltage differential signaling for reliable high-speed data transfer
41
describe the process of sending data through the QPI protocol layers
1. protocol layer - detrmines the packet as a data transfer & adds a protcol header specifying the type and required response
2. routing layer - determines the best path to core B, adding a routing header specifying the destination
3. link layer - splits packet into flits & adds a CRC for reliability
4. physical layer - converts fits into electrical signals & sends them accross QPI lanes to core B
42
describe the process of recieving data through the QPI protocol layers
1. physical layer - recieves signals & converts them into flits
2. link layer - checks for transmission errors using CRC & reassables flits into a full packet
3. routing layer - reads the routing header to confirm the packet is for core B
4. protocol layer - reads the protocol header to determine how to handle the data & extracts abd delivers the data payload to application
43
define PCI
high-bandwidth, proccessor-independent bus for peripheral devices
44
define PCI express
- replaces PCI with a P2P interconnect for higher data rates
- supports high-speed I/O devices
- prioritises real-time data streams
- handles multiple concurrent high-speed transfers efficiently
- PCIe remains standard for GPU, SSDs network cards & expansion cards
45
what 2 things make up the PCIe architecture
1. chipset
2. switch
46
define the PCIe chipset
- connects CPU and memory to PCIe devices
- manages data speed differences and converts signals
- has multiple PCIe ports, some direct, others via a switch
47
define the PCIe switch
- handles multiple PCIe data streams efficiently
48
what are the 3 PCIe device types
1. PCIe endpoint
2. Legacy endpoint
3. PCIe/PCI bridge
49
what is a PCIe endpoint
standard PCIe devices
- ethernet
- GPU
- disk controller
50
what is a legacy endpoint
older devices adapted to PCIe with outdated features
51
what is a PCIe/PCI bridge
allows older PCI devices to connect with PCIe
52
what are 4 protocol layers in PCIe
1. physical
2. data link
3. transaction
4. software
53
describe the PCIe physical layer
- handles signal transmission & reception
- manages low-level data encoding & error detection
- bidirectional unlike QPI
- data split across lanes for parallel processing
- data transmitted serially
54
descibe PCIe data link layer
- ensures reliable transmission using flow control
- uses DLL packets
- adds 2 fields to transaction layer packets:
- 16-bit sequence number - tracks packets order
- 32-bit link CRC - detects transmission errors
- t each intermediate node:
- if no errors, packet continues to destination
-if errors detected, a NAK (negative acknowledgement) is sent, and the faulty packet is discarded
55
describe PCIe transaction layer
- generates & processes transaction layer packets
- manages data & floe control
- each response has a unique identifier
- while waiting for a response, other PCIe traffic can use the link, improving efficiency
56
describe PCIe software layer
- handles r/w requests
- uses packet-based transactions to communicate with I/O devices
57
