Sequential Logic & Memory Flashcards
Week 5 - 10 (14 cards)
describe the idealised behaviour of hardware respresenting time
why is the idealised chip behaviour not achievable
time dealys - computation, propagation
descripe chip behaviour over time
what is the resulting effect of chip behaviour over time
- combinational chips react ‘immediately’ to their inputs
- facilitated by the decision to track changes only at cycle ends
what is used to neutralise time delays
discrete time - cycle length set to be slightly > maximum time delay
- decide to use the chip’s outputs only at the end of the cycles (time-steps) ignoring what happens within cycles
what is combinational logic
- output depends on the current input
- clock is used to stabalise outputs
describe clocks
- passage of time respresented by a master clock
- 2 phases: tick/tock (low/high)
- frequency of clock = one of the factors involved in the speed of computation
what is the memory specification of a clock
- out(t) = in(t - 1) where t is a discrete time interval
- DFF
draw a combinational logic chip over time graph
what is sequential logic
where the output depends on the current input as well as the circuit’s previous state/past input
draw a sequential logic over time diagram
how does a DFF become a 1-bit register
Mux with DFF output, circuit input & load =1 as inputs
show a diagram of a bit register over time
describe a counter in terms of sequential & combinational logic
reset - PC = 0
incremented by 1 - PC ++
set to a specified value - PC = n
