Flashcards in 1-3_a_20151117234432 Deck (25):
A rudimentary error checking scheme that offers no error correction is know as what?
___ is required for the computer system to electrically recognized that the computer minimum number of memory component has been installed.
___ transfer exactly 64 bits of information at a time.
Standard memory controller
__ manages to memory in chunks of the same size as system bus's data width.
Memory controller that support dual-and triple -channel memory implementation were developed in an effort alleviate the bottleneck between the ___ and ___.
RAM and CPU
Briefly explain the terms single -sided memory and double sided memory.
The two refers to how some memory modules have chips oN one side while others have chips on both sides.
list any 3 types of memory.
DRAMA, EDO DRAMA and FPN DRAMA
What is the meaning of this memory DRAM?
Dynamic Random Access Memory.
____ Is characterized by by its independence from the CPU'S external clock.
How was the name DDR was earn?
Double Data Rate earned it name by doubling the transfer rate of ordinary SDRAM;
T/F. ROM can be define as Read Over Memory?
Explain the why Read Only Memory is called read only?
Because the orginal form of this memory could not be written to.
The system ROM in the original IBM PC contained _____?
Power on self test (POST), BIOS and Cassette Basic.
The _ enables the computer to "pull itself up by it boot straps "or boot .
What is SRAM??
Static radon access memory.
T/F. SRAM does require a refresh signal
___ is also called refresh signal
____ supports memory based on the speed of the front side bus (or the CPU'S QPI) and the memory's form factor.
___ is classically used for cache memory?
Static Random Memory
___ access time come in at 40 nanosecond.
__ is more complex, thus more expensive and access times faster 10 ns?
___ is a memory type that was designed to be twice as fast as ___ memory that operates with the same system clock speed.
DDR3 and DDR2
Why wait states is inserted in DRAM through the Bios setup for faster CPU to enable the same memory as a slower CPU?
Because ADRAM is not sychronized to the frontside bus, u would often have to
__ was the term used to refer to the only form of sychronous DRAM on the market